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<div class="title">Design/core_cm3.h</div>  </div>
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<a href="core__cm3_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/**************************************************************************/</span>
<a name="l00024"></a>00024 <span class="preprocessor">#ifndef __CM3_CORE_H__</span>
<a name="l00025"></a>00025 <span class="preprocessor"></span><span class="preprocessor">#define __CM3_CORE_H__</span>
<a name="l00026"></a>00026 <span class="preprocessor"></span>
<a name="l00062"></a>00062 <span class="comment">/*lint -save */</span>
<a name="l00063"></a>00063 <span class="comment">/*lint -e10  */</span>
<a name="l00064"></a>00064 <span class="comment">/*lint -e530 */</span>
<a name="l00065"></a>00065 <span class="comment">/*lint -e550 */</span>
<a name="l00066"></a>00066 <span class="comment">/*lint -e754 */</span>
<a name="l00067"></a>00067 <span class="comment">/*lint -e750 */</span>
<a name="l00068"></a>00068 <span class="comment">/*lint -e528 */</span>
<a name="l00069"></a>00069 <span class="comment">/*lint -e751 */</span>
<a name="l00070"></a>00070 
<a name="l00071"></a>00071 
<a name="l00080"></a>00080 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00081"></a>00081 <span class="preprocessor"></span> <span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {
<a name="l00082"></a>00082 <span class="preprocessor">#endif </span>
<a name="l00083"></a>00083 <span class="preprocessor"></span>
<a name="l00084"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gac1c1120e9fe082fac8225c60143ac79a">00084</a> <span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       </span>
<a name="l00085"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga9ff7a998d4b8b3c87bfaca6e78607950">00085</a> <span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       </span>
<a name="l00086"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf888c651cd8c93fd25364f9e74306a1c">00086</a> <span class="preprocessor">#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB) </span>
<a name="l00088"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga63ea62503c88acab19fcf3d5743009e3">00088</a> <span class="preprocessor">#define __CORTEX_M                (0x03)                                                       </span>
<a name="l00090"></a>00090 <span class="preprocessor">#include &lt;stdint.h&gt;                           </span><span class="comment">/* Include standard types */</span>
<a name="l00091"></a>00091 
<a name="l00092"></a>00092 <span class="preprocessor">#if defined (__ICCARM__)</span>
<a name="l00093"></a>00093 <span class="preprocessor"></span><span class="preprocessor">  #include &lt;intrinsics.h&gt;</span>                     <span class="comment">/* IAR Intrinsics   */</span>
<a name="l00094"></a>00094 <span class="preprocessor">#endif</span>
<a name="l00095"></a>00095 <span class="preprocessor"></span>
<a name="l00096"></a>00096 
<a name="l00097"></a>00097 <span class="preprocessor">#ifndef __NVIC_PRIO_BITS</span>
<a name="l00098"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">00098</a> <span class="preprocessor"></span><span class="preprocessor">  #define __NVIC_PRIO_BITS    4               </span>
<a name="l00099"></a>00099 <span class="preprocessor">#endif</span>
<a name="l00100"></a>00100 <span class="preprocessor"></span>
<a name="l00101"></a>00101 
<a name="l00102"></a>00102 
<a name="l00103"></a>00103 
<a name="l00110"></a>00110 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00111"></a>00111 <span class="preprocessor"></span><span class="preprocessor">  #define     __I     volatile                </span>
<a name="l00112"></a>00112 <span class="preprocessor">#else</span>
<a name="l00113"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">00113</a> <span class="preprocessor"></span><span class="preprocessor">  #define     __I     volatile const          </span>
<a name="l00114"></a>00114 <span class="preprocessor">#endif</span>
<a name="l00115"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">00115</a> <span class="preprocessor"></span><span class="preprocessor">#define     __O     volatile                  </span>
<a name="l00116"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">00116</a> <span class="preprocessor">#define     __IO    volatile                  </span>
<a name="l00120"></a>00120 <span class="preprocessor"></span><span class="comment">/*******************************************************************************</span>
<a name="l00121"></a>00121 <span class="comment"> *                 Register Abstraction</span>
<a name="l00122"></a>00122 <span class="comment"> ******************************************************************************/</span>
<a name="l00123"></a>00123 
<a name="l00132"></a><a class="code" href="struct_n_v_i_c___type.html">00132</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00133"></a>00133 {
<a name="l00134"></a><a class="code" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f">00134</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISER[8];                      
<a name="l00135"></a><a class="code" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">00135</a>        uint32_t RESERVED0[24];                                   
<a name="l00136"></a><a class="code" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5">00136</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICER[8];                      
<a name="l00137"></a><a class="code" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">00137</a>        uint32_t RSERVED1[24];                                    
<a name="l00138"></a><a class="code" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90">00138</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISPR[8];                      
<a name="l00139"></a><a class="code" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">00139</a>        uint32_t RESERVED2[24];                                   
<a name="l00140"></a><a class="code" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5">00140</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICPR[8];                      
<a name="l00141"></a><a class="code" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">00141</a>        uint32_t RESERVED3[24];                                   
<a name="l00142"></a><a class="code" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11">00142</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IABR[8];                      
<a name="l00143"></a><a class="code" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">00143</a>        uint32_t RESERVED4[56];                                   
<a name="l00144"></a><a class="code" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c">00144</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t  IP[240];                      
<a name="l00145"></a><a class="code" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">00145</a>        uint32_t RESERVED5[644];                                  
<a name="l00146"></a><a class="code" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">00146</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t <a class="code" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">STIR</a>;                         
<a name="l00147"></a>00147 }  <a class="code" href="struct_n_v_i_c___type.html">NVIC_Type</a>;                                                <span class="comment">/* end of group CMSIS_CM3_NVIC */</span>
<a name="l00149"></a>00149 
<a name="l00150"></a>00150 
<a name="l00155"></a><a class="code" href="struct_s_c_b___type.html">00155</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00156"></a>00156 {
<a name="l00157"></a><a class="code" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">00157</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">CPUID</a>;                        
<a name="l00158"></a><a class="code" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">00158</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">ICSR</a>;                         
<a name="l00159"></a><a class="code" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">00159</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">VTOR</a>;                         
<a name="l00160"></a><a class="code" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">00160</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">AIRCR</a>;                        
<a name="l00161"></a><a class="code" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">00161</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCR</a>;                          
<a name="l00162"></a><a class="code" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">00162</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">CCR</a>;                          
<a name="l00163"></a><a class="code" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">00163</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t  SHP[12];                      
<a name="l00164"></a><a class="code" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">00164</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SHCSR</a>;                        
<a name="l00165"></a><a class="code" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">00165</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">CFSR</a>;                         
<a name="l00166"></a><a class="code" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">00166</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">HFSR</a>;                         
<a name="l00167"></a><a class="code" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">00167</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">DFSR</a>;                         
<a name="l00168"></a><a class="code" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">00168</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">MMFAR</a>;                        
<a name="l00169"></a><a class="code" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">00169</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">BFAR</a>;                         
<a name="l00170"></a><a class="code" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">00170</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">AFSR</a>;                         
<a name="l00171"></a><a class="code" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">00171</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t PFR[2];                       
<a name="l00172"></a><a class="code" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">00172</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">DFR</a>;                          
<a name="l00173"></a><a class="code" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">00173</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">ADR</a>;                          
<a name="l00174"></a><a class="code" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976">00174</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t MMFR[4];                      
<a name="l00175"></a><a class="code" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">00175</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t ISAR[5];                      
<a name="l00176"></a>00176 } <a class="code" href="struct_s_c_b___type.html">SCB_Type</a>;                                                
<a name="l00177"></a>00177 
<a name="l00178"></a>00178 <span class="comment">/* SCB CPUID Register Definitions */</span>
<a name="l00179"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga58686b88f94f789d4e6f429fe1ff58cf">00179</a> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos          24                                             </span>
<a name="l00180"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga0932b31faafd47656a03ced75a31d99b">00180</a> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul &lt;&lt; SCB_CPUID_IMPLEMENTER_Pos)          </span>
<a name="l00182"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga104462bd0815391b4044a70bd15d3a71">00182</a> <span class="preprocessor">#define SCB_CPUID_VARIANT_Pos              20                                             </span>
<a name="l00183"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gad358dfbd04300afc1824329d128b99e8">00183</a> <span class="preprocessor">#define SCB_CPUID_VARIANT_Msk              (0xFul &lt;&lt; SCB_CPUID_VARIANT_Pos)               </span>
<a name="l00185"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga705f68eaa9afb042ca2407dc4e4629ac">00185</a> <span class="preprocessor">#define SCB_CPUID_PARTNO_Pos                4                                             </span>
<a name="l00186"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga98e581423ca016680c238c469aba546d">00186</a> <span class="preprocessor">#define SCB_CPUID_PARTNO_Msk               (0xFFFul &lt;&lt; SCB_CPUID_PARTNO_Pos)              </span>
<a name="l00188"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3c3d9071e574de11fb27ba57034838b1">00188</a> <span class="preprocessor">#define SCB_CPUID_REVISION_Pos              0                                             </span>
<a name="l00189"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga2ec0448b6483f77e7f5d08b4b81d85df">00189</a> <span class="preprocessor">#define SCB_CPUID_REVISION_Msk             (0xFul &lt;&lt; SCB_CPUID_REVISION_Pos)              </span>
<a name="l00191"></a>00191 <span class="preprocessor"></span><span class="comment">/* SCB Interrupt Control State Register Definitions */</span>
<a name="l00192"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga750d4b52624a46d71356db4ea769573b">00192</a> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Pos            31                                             </span>
<a name="l00193"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga340e3f79e9c3607dee9f2c048b6b22e8">00193</a> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Msk            (1ul &lt;&lt; SCB_ICSR_NMIPENDSET_Pos)               </span>
<a name="l00195"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab5ded23d2ab1d5ff7cc7ce746205e9fe">00195</a> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Pos             28                                             </span>
<a name="l00196"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga1e40d93efb402763c8c00ddcc56724ff">00196</a> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Msk             (1ul &lt;&lt; SCB_ICSR_PENDSVSET_Pos)                </span>
<a name="l00198"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gae218d9022288f89faf57187c4d542ecd">00198</a> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Pos             27                                             </span>
<a name="l00199"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga4a901ace381d3c1c74ac82b22fae2e1e">00199</a> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Msk             (1ul &lt;&lt; SCB_ICSR_PENDSVCLR_Pos)                </span>
<a name="l00201"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga9dbb3358c6167c9c3f85661b90fb2794">00201</a> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Pos             26                                             </span>
<a name="l00202"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga7325b61ea0ec323ef2d5c893b112e546">00202</a> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Msk             (1ul &lt;&lt; SCB_ICSR_PENDSTSET_Pos)                </span>
<a name="l00204"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gadbe25e4b333ece1341beb1a740168fdc">00204</a> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Pos             25                                             </span>
<a name="l00205"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab241827d2a793269d8cd99b9b28c2157">00205</a> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Msk             (1ul &lt;&lt; SCB_ICSR_PENDSTCLR_Pos)                </span>
<a name="l00207"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga11cb5b1f9ce167b81f31787a77e575df">00207</a> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Pos            23                                             </span>
<a name="l00208"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaa966600396290808d596fe96e92ca2b5">00208</a> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Msk            (1ul &lt;&lt; SCB_ICSR_ISRPREEMPT_Pos)               </span>
<a name="l00210"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga10749d92b9b744094b845c2eb46d4319">00210</a> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Pos            22                                             </span>
<a name="l00211"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga056d74fd538e5d36d3be1f28d399c877">00211</a> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Msk            (1ul &lt;&lt; SCB_ICSR_ISRPENDING_Pos)               </span>
<a name="l00213"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gada60c92bf88d6fd21a8f49efa4a127b8">00213</a> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Pos           12                                             </span>
<a name="l00214"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gacb6992e7c7ddc27a370f62878a21ef72">00214</a> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul &lt;&lt; SCB_ICSR_VECTPENDING_Pos)          </span>
<a name="l00216"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga403d154200242629e6d2764bfc12a7ec">00216</a> <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Pos             11                                             </span>
<a name="l00217"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaca6fc3f79bb550f64fd7df782ed4a5f6">00217</a> <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Msk             (1ul &lt;&lt; SCB_ICSR_RETTOBASE_Pos)                </span>
<a name="l00219"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gae4f602c7c5c895d5fb687b71b0979fc3">00219</a> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Pos             0                                             </span>
<a name="l00220"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga5533791a4ecf1b9301c883047b3e8396">00220</a> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul &lt;&lt; SCB_ICSR_VECTACTIVE_Pos)           </span>
<a name="l00222"></a>00222 <span class="preprocessor"></span><span class="comment">/* SCB Interrupt Control State Register Definitions */</span>
<a name="l00223"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gad9720a44320c053883d03b883b955751">00223</a> <span class="preprocessor">#define SCB_VTOR_TBLBASE_Pos               29                                             </span>
<a name="l00224"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga778dd0ba178466b2a8877a6b8aa345ee">00224</a> <span class="preprocessor">#define SCB_VTOR_TBLBASE_Msk               (0x1FFul &lt;&lt; SCB_VTOR_TBLBASE_Pos)              </span>
<a name="l00226"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gac6a55451ddd38bffcff5a211d29cea78">00226</a> <span class="preprocessor">#define SCB_VTOR_TBLOFF_Pos                 7                                             </span>
<a name="l00227"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga75e395ed74042923e8c93edf50f0996c">00227</a> <span class="preprocessor">#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul &lt;&lt; SCB_VTOR_TBLOFF_Pos)            </span>
<a name="l00229"></a>00229 <span class="preprocessor"></span><span class="comment">/* SCB Application Interrupt and Reset Control Register Definitions */</span>
<a name="l00230"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">00230</a> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Pos              16                                             </span>
<a name="l00231"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22">00231</a> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul &lt;&lt; SCB_AIRCR_VECTKEY_Pos)            </span>
<a name="l00233"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaec404750ff5ca07f499a3c06b62051ef">00233</a> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             </span>
<a name="l00234"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gabacedaefeefc73d666bbe59ece904493">00234</a> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul &lt;&lt; SCB_AIRCR_VECTKEYSTAT_Pos)        </span>
<a name="l00236"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gad31dec98fbc0d33ace63cb1f1a927923">00236</a> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Pos            15                                             </span>
<a name="l00237"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga2f571f93d3d4a6eac9a3040756d3d951">00237</a> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Msk            (1ul &lt;&lt; SCB_AIRCR_ENDIANESS_Pos)               </span>
<a name="l00239"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8">00239</a> <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Pos              8                                             </span>
<a name="l00240"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">00240</a> <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Msk             (7ul &lt;&lt; SCB_AIRCR_PRIGROUP_Pos)                </span>
<a name="l00242"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaffb2737eca1eac0fc1c282a76a40953c">00242</a> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             </span>
<a name="l00243"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">00243</a> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul &lt;&lt; SCB_AIRCR_SYSRESETREQ_Pos)             </span>
<a name="l00245"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaa30a12e892bb696e61626d71359a9029">00245</a> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             </span>
<a name="l00246"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga212c5ab1c1c82c807d30d2307aa8d218">00246</a> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul &lt;&lt; SCB_AIRCR_VECTCLRACTIVE_Pos)           </span>
<a name="l00248"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga0d483d9569cd9d1b46ec0d171b1f18d8">00248</a> <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Pos             0                                             </span>
<a name="l00249"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3006e31968bb9725e7b4ee0784d99f7f">00249</a> <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Msk            (1ul &lt;&lt; SCB_AIRCR_VECTRESET_Pos)               </span>
<a name="l00251"></a>00251 <span class="preprocessor"></span><span class="comment">/* SCB System Control Register Definitions */</span>
<a name="l00252"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3bddcec40aeaf3d3a998446100fa0e44">00252</a> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Pos               4                                             </span>
<a name="l00253"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gafb98656644a14342e467505f69a997c9">00253</a> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Msk              (1ul &lt;&lt; SCB_SCR_SEVONPEND_Pos)                 </span>
<a name="l00255"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab304f6258ec03bd9a6e7a360515c3cfe">00255</a> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Pos               2                                             </span>
<a name="l00256"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga77c06a69c63f4b3f6ec1032e911e18e7">00256</a> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Msk              (1ul &lt;&lt; SCB_SCR_SLEEPDEEP_Pos)                 </span>
<a name="l00258"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3680a15114d7fdc1e25043b881308fe9">00258</a> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Pos             1                                             </span>
<a name="l00259"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga50a243e317b9a70781b02758d45b05ee">00259</a> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Msk            (1ul &lt;&lt; SCB_SCR_SLEEPONEXIT_Pos)               </span>
<a name="l00261"></a>00261 <span class="preprocessor"></span><span class="comment">/* SCB Configuration Control Register Definitions */</span>
<a name="l00262"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gac2d20a250960a432cc74da59d20e2f86">00262</a> <span class="preprocessor">#define SCB_CCR_STKALIGN_Pos                9                                             </span>
<a name="l00263"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga33cf22d3d46af158a03aad25ddea1bcb">00263</a> <span class="preprocessor">#define SCB_CCR_STKALIGN_Msk               (1ul &lt;&lt; SCB_CCR_STKALIGN_Pos)                  </span>
<a name="l00265"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga4010a4f9e2a745af1b58abe1f791ebbf">00265</a> <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Pos               8                                             </span>
<a name="l00266"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga89a28cc31cfc7d52d9d7a8fcc69c7eac">00266</a> <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Msk              (1ul &lt;&lt; SCB_CCR_BFHFNMIGN_Pos)                 </span>
<a name="l00268"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gac8d512998bb8cd9333fb7627ddf59bba">00268</a> <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Pos               4                                             </span>
<a name="l00269"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gabb9aeac71b3abd8586d0297070f61dcb">00269</a> <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Msk              (1ul &lt;&lt; SCB_CCR_DIV_0_TRP_Pos)                 </span>
<a name="l00271"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gac4e4928b864ea10fc24dbbc57d976229">00271</a> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Pos             3                                             </span>
<a name="l00272"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga68c96ad594af70c007923979085c99e0">00272</a> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Msk            (1ul &lt;&lt; SCB_CCR_UNALIGN_TRP_Pos)               </span>
<a name="l00274"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga789e41f45f59a8cd455fd59fa7652e5e">00274</a> <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Pos            1                                             </span>
<a name="l00275"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga4cf59b6343ca962c80e1885710da90aa">00275</a> <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Msk           (1ul &lt;&lt; SCB_CCR_USERSETMPEND_Pos)              </span>
<a name="l00277"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab4615f7deb07386350365b10240a3c83">00277</a> <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Pos          0                                             </span>
<a name="l00278"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gafe0f6be81b35d72d0736a0a1e3b4fbb3">00278</a> <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Msk         (1ul &lt;&lt; SCB_CCR_NONBASETHRDENA_Pos)            </span>
<a name="l00280"></a>00280 <span class="preprocessor"></span><span class="comment">/* SCB System Handler Control and State Register Definitions */</span>
<a name="l00281"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gae71949507636fda388ec11d5c2d30b52">00281</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Pos          18                                             </span>
<a name="l00282"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga056fb6be590857bbc029bed48b21dd79">00282</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Msk          (1ul &lt;&lt; SCB_SHCSR_USGFAULTENA_Pos)             </span>
<a name="l00284"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3d32edbe4a5c0335f808cfc19ec7e844">00284</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             </span>
<a name="l00285"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga43e8cbe619c9980e0d1aacc85d9b9e47">00285</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul &lt;&lt; SCB_SHCSR_BUSFAULTENA_Pos)             </span>
<a name="l00287"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga685b4564a8760b4506f14ec4307b7251">00287</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             </span>
<a name="l00288"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaf084424fa1f69bea36a1c44899d83d17">00288</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul &lt;&lt; SCB_SHCSR_MEMFAULTENA_Pos)             </span>
<a name="l00290"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga2f93ec9b243f94cdd3e94b8f0bf43641">00290</a> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             </span>
<a name="l00291"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga6095a7acfbad66f52822b1392be88652">00291</a> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul &lt;&lt; SCB_SHCSR_SVCALLPENDED_Pos)            </span>
<a name="l00293"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaa22551e24a72b65f1e817f7ab462203b">00293</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             </span>
<a name="l00294"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga677c23749c4d348f30fb471d1223e783">00294</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul &lt;&lt; SCB_SHCSR_BUSFAULTPENDED_Pos)          </span>
<a name="l00296"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaceb60fe2d8a8cb17fcd1c1f6b5aa924f">00296</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             </span>
<a name="l00297"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga9abc6c2e395f9e5af4ce05fc420fb04c">00297</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul &lt;&lt; SCB_SHCSR_MEMFAULTPENDED_Pos)          </span>
<a name="l00299"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3cf03acf1fdc2edc3b047ddd47ebbf87">00299</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             </span>
<a name="l00300"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga122b4f732732010895e438803a29d3cc">00300</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul &lt;&lt; SCB_SHCSR_USGFAULTPENDED_Pos)          </span>
<a name="l00302"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaec9ca3b1213c49e2442373445e1697de">00302</a> <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Pos           11                                             </span>
<a name="l00303"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gafef530088dc6d6bfc9f1893d52853684">00303</a> <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Msk           (1ul &lt;&lt; SCB_SHCSR_SYSTICKACT_Pos)              </span>
<a name="l00305"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga9b9fa69ce4c5ce7fe0861dbccfb15939">00305</a> <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Pos            10                                             </span>
<a name="l00306"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gae0e837241a515d4cbadaaae1faa8e039">00306</a> <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Msk            (1ul &lt;&lt; SCB_SHCSR_PENDSVACT_Pos)               </span>
<a name="l00308"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga8b71cf4c61803752a41c96deb00d26af">00308</a> <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Pos            8                                             </span>
<a name="l00309"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaad09b4bc36e9bccccc2e110d20b16e1a">00309</a> <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Msk           (1ul &lt;&lt; SCB_SHCSR_MONITORACT_Pos)              </span>
<a name="l00311"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga977f5176be2bc8b123873861b38bc02f">00311</a> <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Pos             7                                             </span>
<a name="l00312"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga634c0f69a233475289023ae5cb158fdf">00312</a> <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Msk            (1ul &lt;&lt; SCB_SHCSR_SVCALLACT_Pos)               </span>
<a name="l00314"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gae06f54f5081f01ed3f6824e451ad3656">00314</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Pos           3                                             </span>
<a name="l00315"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab3166103b5a5f7931d0df90949c47dfe">00315</a> <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Msk          (1ul &lt;&lt; SCB_SHCSR_USGFAULTACT_Pos)             </span>
<a name="l00317"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaf272760f2df9ecdd8a5fbbd65c0b767a">00317</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             </span>
<a name="l00318"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga9d7a8b1054b655ad08d85c3c535d4f73">00318</a> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul &lt;&lt; SCB_SHCSR_BUSFAULTACT_Pos)             </span>
<a name="l00320"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga7c856f79a75dcc1d1517b19a67691803">00320</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             </span>
<a name="l00321"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga9147fd4e1b12394ae26eadf900a023a3">00321</a> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul &lt;&lt; SCB_SHCSR_MEMFAULTACT_Pos)             </span>
<a name="l00323"></a>00323 <span class="preprocessor"></span><span class="comment">/* SCB Configurable Fault Status Registers Definitions */</span>
<a name="l00324"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gac8e4197b295c8560e68e2d71285c7879">00324</a> <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Pos            16                                             </span>
<a name="l00325"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga565807b1a3f31891f1f967d0fa30d03f">00325</a> <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul &lt;&lt; SCB_CFSR_USGFAULTSR_Pos)          </span>
<a name="l00327"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga555a24f4f57d199f91d1d1ab7c8c3c8a">00327</a> <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Pos             8                                             </span>
<a name="l00328"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga26dc1ddfdc37a6b92597a6f7e498c1d6">00328</a> <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul &lt;&lt; SCB_CFSR_BUSFAULTSR_Pos)            </span>
<a name="l00330"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga91f41491cec5b5acca3fbc94efbd799e">00330</a> <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Pos             0                                             </span>
<a name="l00331"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gad46716159a3808c9e7da22067d6bec98">00331</a> <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul &lt;&lt; SCB_CFSR_MEMFAULTSR_Pos)            </span>
<a name="l00333"></a>00333 <span class="preprocessor"></span><span class="comment">/* SCB Hard Fault Status Registers Definitions */</span>
<a name="l00334"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga300c90cfb7b35c82b4d44ad16c757ffb">00334</a> <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Pos              31                                             </span>
<a name="l00335"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gababd60e94756bb33929d5e6f25d8dba3">00335</a> <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Msk              (1ul &lt;&lt; SCB_HFSR_DEBUGEVT_Pos)                 </span>
<a name="l00337"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gab361e54183a378474cb419ae2a55d6f4">00337</a> <span class="preprocessor">#define SCB_HFSR_FORCED_Pos                30                                             </span>
<a name="l00338"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga6560d97ed043bc01152a7247bafa3157">00338</a> <span class="preprocessor">#define SCB_HFSR_FORCED_Msk                (1ul &lt;&lt; SCB_HFSR_FORCED_Pos)                   </span>
<a name="l00340"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga77993da8de35adea7bda6a4475f036ab">00340</a> <span class="preprocessor">#define SCB_HFSR_VECTTBL_Pos                1                                             </span>
<a name="l00341"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaac5e289211d0a63fe879a9691cb9e1a9">00341</a> <span class="preprocessor">#define SCB_HFSR_VECTTBL_Msk               (1ul &lt;&lt; SCB_HFSR_VECTTBL_Pos)                  </span>
<a name="l00343"></a>00343 <span class="preprocessor"></span><span class="comment">/* SCB Debug Fault Status Register Definitions */</span>
<a name="l00344"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga13f502fb5ac673df9c287488c40b0c1d">00344</a> <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Pos               4                                             </span>
<a name="l00345"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3cba2ec1f588ce0b10b191d6b0d23399">00345</a> <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Msk              (1ul &lt;&lt; SCB_DFSR_EXTERNAL_Pos)                 </span>
<a name="l00347"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gad02d3eaf062ac184c18a7889c9b6de57">00347</a> <span class="preprocessor">#define SCB_DFSR_VCATCH_Pos                 3                                             </span>
<a name="l00348"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gacbb931575c07b324ec793775b7c44d05">00348</a> <span class="preprocessor">#define SCB_DFSR_VCATCH_Msk                (1ul &lt;&lt; SCB_DFSR_VCATCH_Pos)                   </span>
<a name="l00350"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaccf82364c6d0ed7206f1084277b7cc61">00350</a> <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Pos                2                                             </span>
<a name="l00351"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga3f7384b8a761704655fd45396a305663">00351</a> <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Msk               (1ul &lt;&lt; SCB_DFSR_DWTTRAP_Pos)                  </span>
<a name="l00353"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaf28fdce48655f0dcefb383aebf26b050">00353</a> <span class="preprocessor">#define SCB_DFSR_BKPT_Pos                   1                                             </span>
<a name="l00354"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga609edf8f50bc49adb51ae28bcecefe1f">00354</a> <span class="preprocessor">#define SCB_DFSR_BKPT_Msk                  (1ul &lt;&lt; SCB_DFSR_BKPT_Pos)                     </span>
<a name="l00356"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaef4ec28427f9f88ac70a13ae4e541378">00356</a> <span class="preprocessor">#define SCB_DFSR_HALTED_Pos                 0                                             </span>
<a name="l00357"></a><a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga200bcf918d57443b5e29e8ce552e4bdf">00357</a> <span class="preprocessor">#define SCB_DFSR_HALTED_Msk                (1ul &lt;&lt; SCB_DFSR_HALTED_Pos)                   </span>
<a name="l00358"></a>00358 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_SCB */</span>
<a name="l00359"></a>00359 
<a name="l00360"></a>00360 
<a name="l00365"></a><a class="code" href="struct_sys_tick___type.html">00365</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00366"></a>00366 {
<a name="l00367"></a><a class="code" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">00367</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">CTRL</a>;                         
<a name="l00368"></a><a class="code" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">00368</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">LOAD</a>;                         
<a name="l00369"></a><a class="code" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">00369</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">VAL</a>;                          
<a name="l00370"></a><a class="code" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">00370</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">CALIB</a>;                        
<a name="l00371"></a>00371 } <a class="code" href="struct_sys_tick___type.html">SysTick_Type</a>;
<a name="l00372"></a>00372 
<a name="l00373"></a>00373 <span class="comment">/* SysTick Control / Status Register Definitions */</span>
<a name="l00374"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gadbb65d4a815759649db41df216ed4d60">00374</a> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Pos         16                                             </span>
<a name="l00375"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga1bf3033ecccf200f59baefe15dbb367c">00375</a> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Msk         (1ul &lt;&lt; SysTick_CTRL_COUNTFLAG_Pos)            </span>
<a name="l00377"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga24fbc69a5f0b78d67fda2300257baff1">00377</a> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Pos          2                                             </span>
<a name="l00378"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gaa41d06039797423a46596bd313d57373">00378</a> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Msk         (1ul &lt;&lt; SysTick_CTRL_CLKSOURCE_Pos)            </span>
<a name="l00380"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga88f45bbb89ce8df3cd2b2613c7b48214">00380</a> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Pos            1                                             </span>
<a name="l00381"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga95bb984266ca764024836a870238a027">00381</a> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Msk           (1ul &lt;&lt; SysTick_CTRL_TICKINT_Pos)              </span>
<a name="l00383"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga0b48cc1e36d92a92e4bf632890314810">00383</a> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Pos             0                                             </span>
<a name="l00384"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">00384</a> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Msk            (1ul &lt;&lt; SysTick_CTRL_ENABLE_Pos)               </span>
<a name="l00386"></a>00386 <span class="preprocessor"></span><span class="comment">/* SysTick Reload Register Definitions */</span>
<a name="l00387"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gaf44d10df359dc5bf5752b0894ae3bad2">00387</a> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Pos             0                                             </span>
<a name="l00388"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">00388</a> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul &lt;&lt; SysTick_LOAD_RELOAD_Pos)        </span>
<a name="l00390"></a>00390 <span class="preprocessor"></span><span class="comment">/* SysTick Current Register Definitions */</span>
<a name="l00391"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga3208104c3b019b5de35ae8c21d5c34dd">00391</a> <span class="preprocessor">#define SysTick_VAL_CURRENT_Pos             0                                             </span>
<a name="l00392"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gafc77b56d568930b49a2474debc75ab45">00392</a> <span class="preprocessor">#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul &lt;&lt; SysTick_VAL_CURRENT_Pos)        </span>
<a name="l00394"></a>00394 <span class="preprocessor"></span><span class="comment">/* SysTick Calibration Register Definitions */</span>
<a name="l00395"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga534dbe414e7a46a6ce4c1eca1fbff409">00395</a> <span class="preprocessor">#define SysTick_CALIB_NOREF_Pos            31                                             </span>
<a name="l00396"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga3af0d891fdd99bcc8d8912d37830edb6">00396</a> <span class="preprocessor">#define SysTick_CALIB_NOREF_Msk            (1ul &lt;&lt; SysTick_CALIB_NOREF_Pos)               </span>
<a name="l00398"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gadd0c9cd6641b9f6a0c618e7982954860">00398</a> <span class="preprocessor">#define SysTick_CALIB_SKEW_Pos             30                                             </span>
<a name="l00399"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga8a6a85a87334776f33d77fd147587431">00399</a> <span class="preprocessor">#define SysTick_CALIB_SKEW_Msk             (1ul &lt;&lt; SysTick_CALIB_SKEW_Pos)                </span>
<a name="l00401"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gacae558f6e75a0bed5d826f606d8e695e">00401</a> <span class="preprocessor">#define SysTick_CALIB_TENMS_Pos             0                                             </span>
<a name="l00402"></a><a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gaf1e68865c5aece2ad58971225bd3e95e">00402</a> <span class="preprocessor">#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul &lt;&lt; SysTick_VAL_CURRENT_Pos)        </span>
<a name="l00403"></a>00403 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_SysTick */</span>
<a name="l00404"></a>00404 
<a name="l00405"></a>00405 
<a name="l00410"></a><a class="code" href="struct_i_t_m___type.html">00410</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00411"></a>00411 {
<a name="l00412"></a>00412   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  <span class="keyword">union  </span>
<a name="l00413"></a>00413   {
<a name="l00414"></a><a class="code" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">00414</a>     <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  uint8_t    <a class="code" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">u8</a>;                       
<a name="l00415"></a><a class="code" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">00415</a>     <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  uint16_t   <a class="code" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">u16</a>;                      
<a name="l00416"></a><a class="code" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">00416</a>     <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t   <a class="code" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">u32</a>;                      
<a name="l00417"></a>00417   }  PORT [32];                               
<a name="l00418"></a><a class="code" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">00418</a>        uint32_t RESERVED0[864];                                 
<a name="l00419"></a><a class="code" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">00419</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">TER</a>;                          
<a name="l00420"></a><a class="code" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">00420</a>        uint32_t RESERVED1[15];                                  
<a name="l00421"></a><a class="code" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">00421</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">TPR</a>;                          
<a name="l00422"></a><a class="code" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">00422</a>        uint32_t RESERVED2[15];                                  
<a name="l00423"></a><a class="code" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">00423</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">TCR</a>;                          
<a name="l00424"></a><a class="code" href="struct_i_t_m___type.html#ab7708f0bcbbe9987cceadc4748c7e6b7">00424</a>        uint32_t RESERVED3[29];                                  
<a name="l00425"></a><a class="code" href="struct_i_t_m___type.html#af53499fc94cda629afb2fec858d2ad1c">00425</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#af53499fc94cda629afb2fec858d2ad1c">IWR</a>;                          
<a name="l00426"></a><a class="code" href="struct_i_t_m___type.html#ae43a66174b8ab182ff595e5f5da9f235">00426</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#ae43a66174b8ab182ff595e5f5da9f235">IRR</a>;                          
<a name="l00427"></a><a class="code" href="struct_i_t_m___type.html#ab2e87d8bb0e3ce9b8e0e4a6a6695228a">00427</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#ab2e87d8bb0e3ce9b8e0e4a6a6695228a">IMCR</a>;                         
<a name="l00428"></a><a class="code" href="struct_i_t_m___type.html#a45ad0b376a0a0f2ade55bbb7daf64ff2">00428</a>        uint32_t RESERVED4[43];                                  
<a name="l00429"></a><a class="code" href="struct_i_t_m___type.html#a33025af19748bd3ca5cf9d6b14150001">00429</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a33025af19748bd3ca5cf9d6b14150001">LAR</a>;                          
<a name="l00430"></a><a class="code" href="struct_i_t_m___type.html#a56f607260c4175c5f37a28e47ab3d1e5">00430</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a56f607260c4175c5f37a28e47ab3d1e5">LSR</a>;                          
<a name="l00431"></a><a class="code" href="struct_i_t_m___type.html#a7f70161bc2441d430b5c9d55aa7b7b5e">00431</a>        uint32_t RESERVED5[6];                                   
<a name="l00432"></a><a class="code" href="struct_i_t_m___type.html#accfc7de00b0eaba0301e8f4553f70512">00432</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#accfc7de00b0eaba0301e8f4553f70512">PID4</a>;                         
<a name="l00433"></a><a class="code" href="struct_i_t_m___type.html#a9353055ceb7024e07d59248e54502cb9">00433</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a9353055ceb7024e07d59248e54502cb9">PID5</a>;                         
<a name="l00434"></a><a class="code" href="struct_i_t_m___type.html#a755c0ec919e7dbb5f7ff05c8b56a3383">00434</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a755c0ec919e7dbb5f7ff05c8b56a3383">PID6</a>;                         
<a name="l00435"></a><a class="code" href="struct_i_t_m___type.html#aa31ca6bb4b749201321b23d0dbbe0704">00435</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#aa31ca6bb4b749201321b23d0dbbe0704">PID7</a>;                         
<a name="l00436"></a><a class="code" href="struct_i_t_m___type.html#ab69ade751350a7758affdfe396517535">00436</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#ab69ade751350a7758affdfe396517535">PID0</a>;                         
<a name="l00437"></a><a class="code" href="struct_i_t_m___type.html#a30e87ec6f93ecc9fe4f135ca8b068990">00437</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a30e87ec6f93ecc9fe4f135ca8b068990">PID1</a>;                         
<a name="l00438"></a><a class="code" href="struct_i_t_m___type.html#ae139d2e588bb382573ffcce3625a88cd">00438</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#ae139d2e588bb382573ffcce3625a88cd">PID2</a>;                         
<a name="l00439"></a><a class="code" href="struct_i_t_m___type.html#af006ee26c7e61c9a3712a80ac74a6cf3">00439</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#af006ee26c7e61c9a3712a80ac74a6cf3">PID3</a>;                         
<a name="l00440"></a><a class="code" href="struct_i_t_m___type.html#a413f3bb0a15222e5f38fca4baeef14f6">00440</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a413f3bb0a15222e5f38fca4baeef14f6">CID0</a>;                         
<a name="l00441"></a><a class="code" href="struct_i_t_m___type.html#a5f7d524b71f49e444ff0d1d52b3c3565">00441</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a5f7d524b71f49e444ff0d1d52b3c3565">CID1</a>;                         
<a name="l00442"></a><a class="code" href="struct_i_t_m___type.html#adee4ccce1429db8b5db3809c4539f876">00442</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#adee4ccce1429db8b5db3809c4539f876">CID2</a>;                         
<a name="l00443"></a><a class="code" href="struct_i_t_m___type.html#a0e7aa199619cc7ac6baddff9600aa52e">00443</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_i_t_m___type.html#a0e7aa199619cc7ac6baddff9600aa52e">CID3</a>;                         
<a name="l00444"></a>00444 } <a class="code" href="struct_i_t_m___type.html">ITM_Type</a>;                                                
<a name="l00445"></a>00445 
<a name="l00446"></a>00446 <span class="comment">/* ITM Trace Privilege Register Definitions */</span>
<a name="l00447"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga7abe5e590d1611599df87a1884a352e8">00447</a> <span class="preprocessor">#define ITM_TPR_PRIVMASK_Pos                0                                             </span>
<a name="l00448"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga168e089d882df325a387aab3a802a46b">00448</a> <span class="preprocessor">#define ITM_TPR_PRIVMASK_Msk               (0xFul &lt;&lt; ITM_TPR_PRIVMASK_Pos)                </span>
<a name="l00450"></a>00450 <span class="preprocessor"></span><span class="comment">/* ITM Trace Control Register Definitions */</span>
<a name="l00451"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga9174ad4a36052c377cef4e6aba2ed484">00451</a> <span class="preprocessor">#define ITM_TCR_BUSY_Pos                   23                                             </span>
<a name="l00452"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga43ad7cf33de12f2ef3a412d4f354c60f">00452</a> <span class="preprocessor">#define ITM_TCR_BUSY_Msk                   (1ul &lt;&lt; ITM_TCR_BUSY_Pos)                      </span>
<a name="l00454"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gad5a179af7ad1f2b8958e50907186529b">00454</a> <span class="preprocessor">#define ITM_TCR_ATBID_Pos                  16                                             </span>
<a name="l00455"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga491d8bddbe6c0523ff10ef6d2846f0f2">00455</a> <span class="preprocessor">#define ITM_TCR_ATBID_Msk                  (0x7Ful &lt;&lt; ITM_TCR_ATBID_Pos)                  </span>
<a name="l00457"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gad7bc9ee1732032c6e0de035f0978e473">00457</a> <span class="preprocessor">#define ITM_TCR_TSPrescale_Pos              8                                             </span>
<a name="l00458"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga7a723f71bfb0204c264d8dbe8cc7ae52">00458</a> <span class="preprocessor">#define ITM_TCR_TSPrescale_Msk             (3ul &lt;&lt; ITM_TCR_TSPrescale_Pos)                </span>
<a name="l00460"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga7a380f0c8078f6560051406583ecd6a5">00460</a> <span class="preprocessor">#define ITM_TCR_SWOENA_Pos                  4                                             </span>
<a name="l00461"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga97476cb65bab16a328b35f81fd02010a">00461</a> <span class="preprocessor">#define ITM_TCR_SWOENA_Msk                 (1ul &lt;&lt; ITM_TCR_SWOENA_Pos)                    </span>
<a name="l00463"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga30e83ebb33aa766070fe3d1f27ae820e">00463</a> <span class="preprocessor">#define ITM_TCR_DWTENA_Pos                  3                                             </span>
<a name="l00464"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga98ea1c596d43d3633a202f9ee746cf70">00464</a> <span class="preprocessor">#define ITM_TCR_DWTENA_Msk                 (1ul &lt;&lt; ITM_TCR_DWTENA_Pos)                    </span>
<a name="l00466"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gaa93a1147a39fc63980d299231252a30e">00466</a> <span class="preprocessor">#define ITM_TCR_SYNCENA_Pos                 2                                             </span>
<a name="l00467"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gac89b74a78701c25b442105d7fe2bbefb">00467</a> <span class="preprocessor">#define ITM_TCR_SYNCENA_Msk                (1ul &lt;&lt; ITM_TCR_SYNCENA_Pos)                   </span>
<a name="l00469"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga5aa381845f810114ab519b90753922a1">00469</a> <span class="preprocessor">#define ITM_TCR_TSENA_Pos                   1                                             </span>
<a name="l00470"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga436b2e8fa24328f48f2da31c00fc9e65">00470</a> <span class="preprocessor">#define ITM_TCR_TSENA_Msk                  (1ul &lt;&lt; ITM_TCR_TSENA_Pos)                     </span>
<a name="l00472"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga3286b86004bce7ffe17ee269f87f8d9d">00472</a> <span class="preprocessor">#define ITM_TCR_ITMENA_Pos                  0                                             </span>
<a name="l00473"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9">00473</a> <span class="preprocessor">#define ITM_TCR_ITMENA_Msk                 (1ul &lt;&lt; ITM_TCR_ITMENA_Pos)                    </span>
<a name="l00475"></a>00475 <span class="preprocessor"></span><span class="comment">/* ITM Integration Write Register Definitions */</span>
<a name="l00476"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga04d3f842ad48f6a9127b4cecc963e1d7">00476</a> <span class="preprocessor">#define ITM_IWR_ATVALIDM_Pos                0                                             </span>
<a name="l00477"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga67b969f8f04ed15886727788f0e2ffd7">00477</a> <span class="preprocessor">#define ITM_IWR_ATVALIDM_Msk               (1ul &lt;&lt; ITM_IWR_ATVALIDM_Pos)                  </span>
<a name="l00479"></a>00479 <span class="preprocessor"></span><span class="comment">/* ITM Integration Read Register Definitions */</span>
<a name="l00480"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga259edfd1d2e877a62e06d7a240df97f4">00480</a> <span class="preprocessor">#define ITM_IRR_ATREADYM_Pos                0                                             </span>
<a name="l00481"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga3dbc3e15f5bde2669cd8121a1fe419b9">00481</a> <span class="preprocessor">#define ITM_IRR_ATREADYM_Msk               (1ul &lt;&lt; ITM_IRR_ATREADYM_Pos)                  </span>
<a name="l00483"></a>00483 <span class="preprocessor"></span><span class="comment">/* ITM Integration Mode Control Register Definitions */</span>
<a name="l00484"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga08de02bf32caf48aaa29f7c68ff5d755">00484</a> <span class="preprocessor">#define ITM_IMCR_INTEGRATION_Pos            0                                             </span>
<a name="l00485"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga8838bd3dd04c1a6be97cd946364a3fd2">00485</a> <span class="preprocessor">#define ITM_IMCR_INTEGRATION_Msk           (1ul &lt;&lt; ITM_IMCR_INTEGRATION_Pos)              </span>
<a name="l00487"></a>00487 <span class="preprocessor"></span><span class="comment">/* ITM Lock Status Register Definitions */</span>
<a name="l00488"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gabfae3e570edc8759597311ed6dfb478e">00488</a> <span class="preprocessor">#define ITM_LSR_ByteAcc_Pos                 2                                             </span>
<a name="l00489"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga91f492b2891bb8b7eac5b58de7b220f4">00489</a> <span class="preprocessor">#define ITM_LSR_ByteAcc_Msk                (1ul &lt;&lt; ITM_LSR_ByteAcc_Pos)                   </span>
<a name="l00491"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga144a49e12b83ad9809fdd2769094fdc0">00491</a> <span class="preprocessor">#define ITM_LSR_Access_Pos                  1                                             </span>
<a name="l00492"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gac8ae69f11c0311da226c0c8ec40b3d37">00492</a> <span class="preprocessor">#define ITM_LSR_Access_Msk                 (1ul &lt;&lt; ITM_LSR_Access_Pos)                    </span>
<a name="l00494"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gaf5740689cf14564d3f3fd91299b6c88d">00494</a> <span class="preprocessor">#define ITM_LSR_Present_Pos                 0                                             </span>
<a name="l00495"></a><a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#gaa5bc2a7f5f1d69ff819531f5508bb017">00495</a> <span class="preprocessor">#define ITM_LSR_Present_Msk                (1ul &lt;&lt; ITM_LSR_Present_Pos)                   </span>
<a name="l00496"></a>00496 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_ITM */</span>
<a name="l00497"></a>00497 
<a name="l00498"></a>00498 
<a name="l00503"></a><a class="code" href="struct_interrupt_type___type.html">00503</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00504"></a>00504 {
<a name="l00505"></a><a class="code" href="struct_interrupt_type___type.html#ae0d588643b0488fce4c0a90b85edf362">00505</a>        uint32_t <a class="code" href="struct_interrupt_type___type.html#ae0d588643b0488fce4c0a90b85edf362">RESERVED0</a>;
<a name="l00506"></a><a class="code" href="struct_interrupt_type___type.html#a2b10f6d37363a6b798ac97f4c4db1e63">00506</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code" href="struct_interrupt_type___type.html#a2b10f6d37363a6b798ac97f4c4db1e63">ICTR</a>;                         
<a name="l00507"></a>00507 <span class="preprocessor">#if ((defined __CM3_REV) &amp;&amp; (__CM3_REV &gt;= 0x200))</span>
<a name="l00508"></a>00508 <span class="preprocessor"></span>  <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ACTLR;                        
<a name="l00509"></a>00509 <span class="preprocessor">#else</span>
<a name="l00510"></a><a class="code" href="struct_interrupt_type___type.html#a45933eb981309d50f943ec3af67f17be">00510</a> <span class="preprocessor"></span>       uint32_t <a class="code" href="struct_interrupt_type___type.html#a45933eb981309d50f943ec3af67f17be">RESERVED1</a>;
<a name="l00511"></a>00511 <span class="preprocessor">#endif</span>
<a name="l00512"></a>00512 <span class="preprocessor"></span>} <a class="code" href="struct_interrupt_type___type.html">InterruptType_Type</a>;
<a name="l00513"></a>00513 
<a name="l00514"></a>00514 <span class="comment">/* Interrupt Controller Type Register Definitions */</span>
<a name="l00515"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga5d164b3cb981bd85afd35892d180a5c3">00515</a> <span class="preprocessor">#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             </span>
<a name="l00516"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga0a2c325cefdab97bd8ce3336a66a803e">00516</a> <span class="preprocessor">#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful &lt;&lt; InterruptType_ICTR_INTLINESNUM_Pos) </span>
<a name="l00518"></a>00518 <span class="preprocessor"></span><span class="comment">/* Auxiliary Control Register Definitions */</span>
<a name="l00519"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#gaaa37f212111e6dbc9505d46b8bf8fa3e">00519</a> <span class="preprocessor">#define InterruptType_ACTLR_DISFOLD_Pos     2                                             </span>
<a name="l00520"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#gac4d872ecfcf7dcb93f98824ada52a527">00520</a> <span class="preprocessor">#define InterruptType_ACTLR_DISFOLD_Msk    (1ul &lt;&lt; InterruptType_ACTLR_DISFOLD_Pos)       </span>
<a name="l00522"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga46fed31841c33811db8b3a9cbae6347b">00522</a> <span class="preprocessor">#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             </span>
<a name="l00523"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga3cecf9e9d75112aed3ed055343cbe23f">00523</a> <span class="preprocessor">#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul &lt;&lt; InterruptType_ACTLR_DISDEFWBUF_Pos)    </span>
<a name="l00525"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga101a93632e4480073299b775bc5cbf12">00525</a> <span class="preprocessor">#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             </span>
<a name="l00526"></a><a class="code" href="group___c_m_s_i_s___c_m3___interrupt_type.html#ga0c020eb28544979bfac2e219ed53c999">00526</a> <span class="preprocessor">#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul &lt;&lt; InterruptType_ACTLR_DISMCYCINT_Pos)    </span>
<a name="l00527"></a>00527 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_InterruptType */</span>
<a name="l00528"></a>00528 
<a name="l00529"></a>00529 
<a name="l00530"></a>00530 <span class="preprocessor">#if defined (__MPU_PRESENT) &amp;&amp; (__MPU_PRESENT == 1)</span>
<a name="l00531"></a>00531 <span class="preprocessor"></span>
<a name="l00535"></a>00535 <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00536"></a>00536 {
<a name="l00537"></a>00537   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaf63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t TYPE;                         
<a name="l00538"></a>00538   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CTRL;                         
<a name="l00539"></a>00539   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RNR;                          
<a name="l00540"></a>00540   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR;                         
<a name="l00541"></a>00541   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR;                         
<a name="l00542"></a>00542   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A1;                      
<a name="l00543"></a>00543   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A1;                      
<a name="l00544"></a>00544   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A2;                      
<a name="l00545"></a>00545   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A2;                      
<a name="l00546"></a>00546   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A3;                      
<a name="l00547"></a>00547   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A3;                      
<a name="l00548"></a>00548 } MPU_Type;                                                
<a name="l00549"></a>00549 
<a name="l00550"></a>00550 <span class="comment">/* MPU Type Register */</span>
<a name="l00551"></a>00551 <span class="preprocessor">#define MPU_TYPE_IREGION_Pos               16                                             </span>
<a name="l00552"></a>00552 <span class="preprocessor">#define MPU_TYPE_IREGION_Msk               (0xFFul &lt;&lt; MPU_TYPE_IREGION_Pos)               </span>
<a name="l00554"></a>00554 <span class="preprocessor">#define MPU_TYPE_DREGION_Pos                8                                             </span>
<a name="l00555"></a>00555 <span class="preprocessor">#define MPU_TYPE_DREGION_Msk               (0xFFul &lt;&lt; MPU_TYPE_DREGION_Pos)               </span>
<a name="l00557"></a>00557 <span class="preprocessor">#define MPU_TYPE_SEPARATE_Pos               0                                             </span>
<a name="l00558"></a>00558 <span class="preprocessor">#define MPU_TYPE_SEPARATE_Msk              (1ul &lt;&lt; MPU_TYPE_SEPARATE_Pos)                 </span>
<a name="l00560"></a>00560 <span class="preprocessor"></span><span class="comment">/* MPU Control Register */</span>
<a name="l00561"></a>00561 <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Pos             2                                             </span>
<a name="l00562"></a>00562 <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Msk            (1ul &lt;&lt; MPU_CTRL_PRIVDEFENA_Pos)               </span>
<a name="l00564"></a>00564 <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Pos               1                                             </span>
<a name="l00565"></a>00565 <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Msk              (1ul &lt;&lt; MPU_CTRL_HFNMIENA_Pos)                 </span>
<a name="l00567"></a>00567 <span class="preprocessor">#define MPU_CTRL_ENABLE_Pos                 0                                             </span>
<a name="l00568"></a>00568 <span class="preprocessor">#define MPU_CTRL_ENABLE_Msk                (1ul &lt;&lt; MPU_CTRL_ENABLE_Pos)                   </span>
<a name="l00570"></a>00570 <span class="preprocessor"></span><span class="comment">/* MPU Region Number Register */</span>
<a name="l00571"></a>00571 <span class="preprocessor">#define MPU_RNR_REGION_Pos                  0                                             </span>
<a name="l00572"></a>00572 <span class="preprocessor">#define MPU_RNR_REGION_Msk                 (0xFFul &lt;&lt; MPU_RNR_REGION_Pos)                 </span>
<a name="l00574"></a>00574 <span class="preprocessor"></span><span class="comment">/* MPU Region Base Address Register */</span>
<a name="l00575"></a>00575 <span class="preprocessor">#define MPU_RBAR_ADDR_Pos                   5                                             </span>
<a name="l00576"></a>00576 <span class="preprocessor">#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul &lt;&lt; MPU_RBAR_ADDR_Pos)             </span>
<a name="l00578"></a>00578 <span class="preprocessor">#define MPU_RBAR_VALID_Pos                  4                                             </span>
<a name="l00579"></a>00579 <span class="preprocessor">#define MPU_RBAR_VALID_Msk                 (1ul &lt;&lt; MPU_RBAR_VALID_Pos)                    </span>
<a name="l00581"></a>00581 <span class="preprocessor">#define MPU_RBAR_REGION_Pos                 0                                             </span>
<a name="l00582"></a>00582 <span class="preprocessor">#define MPU_RBAR_REGION_Msk                (0xFul &lt;&lt; MPU_RBAR_REGION_Pos)                 </span>
<a name="l00584"></a>00584 <span class="preprocessor"></span><span class="comment">/* MPU Region Attribute and Size Register */</span>
<a name="l00585"></a>00585 <span class="preprocessor">#define MPU_RASR_XN_Pos                    28                                             </span>
<a name="l00586"></a>00586 <span class="preprocessor">#define MPU_RASR_XN_Msk                    (1ul &lt;&lt; MPU_RASR_XN_Pos)                       </span>
<a name="l00588"></a>00588 <span class="preprocessor">#define MPU_RASR_AP_Pos                    24                                             </span>
<a name="l00589"></a>00589 <span class="preprocessor">#define MPU_RASR_AP_Msk                    (7ul &lt;&lt; MPU_RASR_AP_Pos)                       </span>
<a name="l00591"></a>00591 <span class="preprocessor">#define MPU_RASR_TEX_Pos                   19                                             </span>
<a name="l00592"></a>00592 <span class="preprocessor">#define MPU_RASR_TEX_Msk                   (7ul &lt;&lt; MPU_RASR_TEX_Pos)                      </span>
<a name="l00594"></a>00594 <span class="preprocessor">#define MPU_RASR_S_Pos                     18                                             </span>
<a name="l00595"></a>00595 <span class="preprocessor">#define MPU_RASR_S_Msk                     (1ul &lt;&lt; MPU_RASR_S_Pos)                        </span>
<a name="l00597"></a>00597 <span class="preprocessor">#define MPU_RASR_C_Pos                     17                                             </span>
<a name="l00598"></a>00598 <span class="preprocessor">#define MPU_RASR_C_Msk                     (1ul &lt;&lt; MPU_RASR_C_Pos)                        </span>
<a name="l00600"></a>00600 <span class="preprocessor">#define MPU_RASR_B_Pos                     16                                             </span>
<a name="l00601"></a>00601 <span class="preprocessor">#define MPU_RASR_B_Msk                     (1ul &lt;&lt; MPU_RASR_B_Pos)                        </span>
<a name="l00603"></a>00603 <span class="preprocessor">#define MPU_RASR_SRD_Pos                    8                                             </span>
<a name="l00604"></a>00604 <span class="preprocessor">#define MPU_RASR_SRD_Msk                   (0xFFul &lt;&lt; MPU_RASR_SRD_Pos)                   </span>
<a name="l00606"></a>00606 <span class="preprocessor">#define MPU_RASR_SIZE_Pos                   1                                             </span>
<a name="l00607"></a>00607 <span class="preprocessor">#define MPU_RASR_SIZE_Msk                  (0x1Ful &lt;&lt; MPU_RASR_SIZE_Pos)                  </span>
<a name="l00609"></a>00609 <span class="preprocessor">#define MPU_RASR_ENA_Pos                     0                                            </span>
<a name="l00610"></a>00610 <span class="preprocessor">#define MPU_RASR_ENA_Msk                    (0x1Ful &lt;&lt; MPU_RASR_ENA_Pos)                  </span>
<a name="l00612"></a>00612 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_MPU */</span>
<a name="l00613"></a>00613 <span class="preprocessor">#endif</span>
<a name="l00614"></a>00614 <span class="preprocessor"></span>
<a name="l00615"></a>00615 
<a name="l00620"></a><a class="code" href="struct_core_debug___type.html">00620</a> <span class="keyword">typedef</span> <span class="keyword">struct</span>
<a name="l00621"></a>00621 {
<a name="l00622"></a><a class="code" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">00622</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">DHCSR</a>;                        
<a name="l00623"></a><a class="code" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">00623</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#ga7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t <a class="code" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">DCRSR</a>;                        
<a name="l00624"></a><a class="code" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">00624</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">DCRDR</a>;                        
<a name="l00625"></a><a class="code" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">00625</a>   <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gaec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">DEMCR</a>;                        
<a name="l00626"></a>00626 } <a class="code" href="struct_core_debug___type.html">CoreDebug_Type</a>;
<a name="l00627"></a>00627 
<a name="l00628"></a>00628 <span class="comment">/* Debug Halting Control and Status Register */</span>
<a name="l00629"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gac91280edd0ce932665cf75a23d11d842">00629</a> <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             </span>
<a name="l00630"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga1ce997cee15edaafe4aed77751816ffc">00630</a> <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul &lt;&lt; CoreDebug_DHCSR_DBGKEY_Pos)       </span>
<a name="l00632"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga6f934c5427ea057394268e541fa97753">00632</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             </span>
<a name="l00633"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gac474394bcceb31a8e09566c90b3f8922">00633</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul &lt;&lt; CoreDebug_DHCSR_S_RESET_ST_Pos)        </span>
<a name="l00635"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga2328118f8b3574c871a53605eb17e730">00635</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             </span>
<a name="l00636"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga89dceb5325f6bcb36a0473d65fbfcfa6">00636</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul &lt;&lt; CoreDebug_DHCSR_S_RETIRE_ST_Pos)       </span>
<a name="l00638"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga2900dd56a988a4ed27ad664d5642807e">00638</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             </span>
<a name="l00639"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga7b67e4506d7f464ef5dafd6219739756">00639</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul &lt;&lt; CoreDebug_DHCSR_S_LOCKUP_Pos)          </span>
<a name="l00641"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga349ccea33accc705595624c2d334fbcb">00641</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             </span>
<a name="l00642"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga98d51538e645c2c1a422279cd85a0a25">00642</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul &lt;&lt; CoreDebug_DHCSR_S_SLEEP_Pos)           </span>
<a name="l00644"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga760a9a0d7f39951dc3f07d01f1f64772">00644</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Pos         17                                             </span>
<a name="l00645"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga9f881ade3151a73bc5b02b73fe6473ca">00645</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Msk         (1ul &lt;&lt; CoreDebug_DHCSR_S_HALT_Pos)            </span>
<a name="l00647"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga20a71871ca8768019c51168c70c3f41d">00647</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             </span>
<a name="l00648"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gac4cd6f3178de48f473d8903e8c847c07">00648</a> <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul &lt;&lt; CoreDebug_DHCSR_S_REGRDY_Pos)          </span>
<a name="l00650"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga85747214e2656df6b05ec72e4d22bd6d">00650</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             </span>
<a name="l00651"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga53aa99b2e39a67622f3b9973e079c2b4">00651</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul &lt;&lt; CoreDebug_DHCSR_C_SNAPSTALL_Pos)       </span>
<a name="l00653"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga0d2907400eb948a4ea3886ca083ec8e3">00653</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             </span>
<a name="l00654"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga77fe1ef3c4a729c1c82fb62a94a51c31">00654</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul &lt;&lt; CoreDebug_DHCSR_C_MASKINTS_Pos)        </span>
<a name="l00656"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gae1fc39e80de54c0339cbb1b298a9f0f9">00656</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Pos          2                                             </span>
<a name="l00657"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gae6bda72fbd32cc5734ff3542170dc00d">00657</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Msk         (1ul &lt;&lt; CoreDebug_DHCSR_C_STEP_Pos)            </span>
<a name="l00659"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gaddf1d43f8857e4efc3dc4e6b15509692">00659</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Pos          1                                             </span>
<a name="l00660"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga1d905a3aa594eb2e8bb78bcc4da05b3f">00660</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Msk         (1ul &lt;&lt; CoreDebug_DHCSR_C_HALT_Pos)            </span>
<a name="l00662"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gab557abb5b172b74d2cf44efb9d824e4e">00662</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             </span>
<a name="l00663"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gab815c741a4fc2a61988cd2fb7594210b">00663</a> <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul &lt;&lt; CoreDebug_DHCSR_C_DEBUGEN_Pos)         </span>
<a name="l00665"></a>00665 <span class="preprocessor"></span><span class="comment">/* Debug Core Register Selector Register */</span>
<a name="l00666"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga51e75942fc0614bc9bb2c0e96fcdda9a">00666</a> <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Pos         16                                             </span>
<a name="l00667"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga1eef4992d8f84bc6c0dffed1c87f90a5">00667</a> <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Msk         (1ul &lt;&lt; CoreDebug_DCRSR_REGWnR_Pos)            </span>
<a name="l00669"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga52182c8a9f63a52470244c0bc2064f7b">00669</a> <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Pos          0                                             </span>
<a name="l00670"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga17cafbd72b55030219ce5609baa7c01d">00670</a> <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful &lt;&lt; CoreDebug_DCRSR_REGSEL_Pos)         </span>
<a name="l00672"></a>00672 <span class="preprocessor"></span><span class="comment">/* Debug Exception and Monitor Control Register */</span>
<a name="l00673"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga6ff2102b98f86540224819a1b767ba39">00673</a> <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Pos         24                                             </span>
<a name="l00674"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga5e99652c1df93b441257389f49407834">00674</a> <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Msk         (1ul &lt;&lt; CoreDebug_DEMCR_TRCENA_Pos)            </span>
<a name="l00676"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga341020a3b7450416d72544eaf8e57a64">00676</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             </span>
<a name="l00677"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gae6384cbe8045051186d13ef9cdeace95">00677</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul &lt;&lt; CoreDebug_DEMCR_MON_REQ_Pos)           </span>
<a name="l00679"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga9ae10710684e14a1a534e785ef390e1b">00679</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             </span>
<a name="l00680"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga2ded814556de96fc369de7ae9a7ceb98">00680</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul &lt;&lt; CoreDebug_DEMCR_MON_STEP_Pos)          </span>
<a name="l00682"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga1e2f706a59e0d8131279af1c7e152f8d">00682</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             </span>
<a name="l00683"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga68ec55930269fab78e733dcfa32392f8">00683</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul &lt;&lt; CoreDebug_DEMCR_MON_PEND_Pos)          </span>
<a name="l00685"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga802829678f6871863ae9ecf60a10425c">00685</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Pos         16                                             </span>
<a name="l00686"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gac2b46b9b65bf8d23027f255fc9641977">00686</a> <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Msk         (1ul &lt;&lt; CoreDebug_DEMCR_MON_EN_Pos)            </span>
<a name="l00688"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gaed9f42053031a9a30cd8054623304c0a">00688</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             </span>
<a name="l00689"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga803fc98c5bb85f10f0347b23794847d1">00689</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul &lt;&lt; CoreDebug_DEMCR_VC_HARDERR_Pos)        </span>
<a name="l00691"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga22079a6e436f23b90308be97e19cf07e">00691</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             </span>
<a name="l00692"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gad6815d8e3df302d2f0ff2c2c734ed29a">00692</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul &lt;&lt; CoreDebug_DEMCR_VC_INTERR_Pos)         </span>
<a name="l00694"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gab8e3d8f0f9590a51bbf10f6da3ad6933">00694</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             </span>
<a name="l00695"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga9d29546aefe3ca8662a7fe48dd4a5b2b">00695</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul &lt;&lt; CoreDebug_DEMCR_VC_BUSERR_Pos)         </span>
<a name="l00697"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga16f0d3d2ce1e1e8cd762d938ac56c4ac">00697</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             </span>
<a name="l00698"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gaa38b947d77672c48bba1280c0a642e19">00698</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul &lt;&lt; CoreDebug_DEMCR_VC_STATERR_Pos)        </span>
<a name="l00700"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga10fc7c53bca904c128bc8e1a03072d50">00700</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             </span>
<a name="l00701"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga2f98b461d19746ab2febfddebb73da6f">00701</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul &lt;&lt; CoreDebug_DEMCR_VC_CHKERR_Pos)         </span>
<a name="l00703"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gac9d13eb2add61f610d5ced1f7ad2adf8">00703</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             </span>
<a name="l00704"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga03ee58b1b02fdbf21612809034562f1c">00704</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul &lt;&lt; CoreDebug_DEMCR_VC_NOCPERR_Pos)        </span>
<a name="l00706"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga444454f7c7748e76cd76c3809c887c41">00706</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             </span>
<a name="l00707"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#gad420a9b60620584faaca6289e83d3a87">00707</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul &lt;&lt; CoreDebug_DEMCR_VC_MMERR_Pos)          </span>
<a name="l00709"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga9fcf09666f7063a7303117aa32a85d5a">00709</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             </span>
<a name="l00710"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga906476e53c1e1487c30f3a1181df9e30">00710</a> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul &lt;&lt; CoreDebug_DEMCR_VC_CORERESET_Pos)      </span>
<a name="l00711"></a>00711 <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_CM3_CoreDebug */</span>
<a name="l00712"></a>00712 
<a name="l00713"></a>00713 
<a name="l00714"></a>00714 <span class="comment">/* Memory mapping of Cortex-M3 Hardware */</span>
<a name="l00715"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#ga3c14ed93192c8d9143322bbf77ebf770">00715</a> <span class="preprocessor">#define SCS_BASE            (0xE000E000)                              </span>
<a name="l00716"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gadd76251e412a195ec0a8f47227a8359e">00716</a> <span class="preprocessor">#define ITM_BASE            (0xE0000000)                              </span>
<a name="l00717"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#ga680604dbcda9e9b31a1639fcffe5230b">00717</a> <span class="preprocessor">#define CoreDebug_BASE      (0xE000EDF0)                              </span>
<a name="l00718"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#ga58effaac0b93006b756d33209e814646">00718</a> <span class="preprocessor">#define SysTick_BASE        (SCS_BASE +  0x0010)                      </span>
<a name="l00719"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaa0288691785a5f868238e0468b39523d">00719</a> <span class="preprocessor">#define NVIC_BASE           (SCS_BASE +  0x0100)                      </span>
<a name="l00720"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd">00720</a> <span class="preprocessor">#define SCB_BASE            (SCS_BASE +  0x0D00)                      </span>
<a name="l00722"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#ga164238adbad56f07c7dd4e912af748dd">00722</a> <span class="preprocessor">#define InterruptType       ((InterruptType_Type *) SCS_BASE)         </span>
<a name="l00723"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">00723</a> <span class="preprocessor">#define SCB                 ((SCB_Type *)           SCB_BASE)         </span>
<a name="l00724"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gacd96c53beeaff8f603fcda425eb295de">00724</a> <span class="preprocessor">#define SysTick             ((SysTick_Type *)       SysTick_BASE)     </span>
<a name="l00725"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">00725</a> <span class="preprocessor">#define NVIC                ((NVIC_Type *)          NVIC_BASE)        </span>
<a name="l00726"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gabae7cdf882def602cb787bb039ff6a43">00726</a> <span class="preprocessor">#define ITM                 ((ITM_Type *)           ITM_BASE)         </span>
<a name="l00727"></a><a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gab6e30a2b802d9021619dbb0be7f5d63d">00727</a> <span class="preprocessor">#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   </span>
<a name="l00729"></a>00729 <span class="preprocessor">#if defined (__MPU_PRESENT) &amp;&amp; (__MPU_PRESENT == 1)</span>
<a name="l00730"></a>00730 <span class="preprocessor"></span><span class="preprocessor">  #define MPU_BASE          (SCS_BASE +  0x0D90)                      </span>
<a name="l00731"></a>00731 <span class="preprocessor">  #define MPU               ((MPU_Type*)            MPU_BASE)         </span>
<a name="l00732"></a>00732 <span class="preprocessor">#endif</span>
<a name="l00733"></a>00733 <span class="preprocessor"></span> <span class="comment">/* end of group CMSIS_CM3_core_register */</span>
<a name="l00735"></a>00735 
<a name="l00736"></a>00736 
<a name="l00737"></a>00737 <span class="comment">/*******************************************************************************</span>
<a name="l00738"></a>00738 <span class="comment"> *                Hardware Abstraction Layer</span>
<a name="l00739"></a>00739 <span class="comment"> ******************************************************************************/</span>
<a name="l00740"></a>00740 
<a name="l00741"></a>00741 <span class="preprocessor">#if defined ( __CC_ARM   )</span>
<a name="l00742"></a>00742 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00743"></a>00743 <span class="preprocessor">  #define __INLINE         __inline                                   </span>
<a name="l00745"></a>00745 <span class="preprocessor">#elif defined ( __ICCARM__ )</span>
<a name="l00746"></a>00746 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM           __asm                                       </span>
<a name="l00747"></a>00747 <span class="preprocessor">  #define __INLINE        inline                                      </span>
<a name="l00749"></a>00749 <span class="preprocessor">#elif defined   (  __GNUC__  )</span>
<a name="l00750"></a>00750 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00751"></a>00751 <span class="preprocessor">  #define __INLINE         inline                                     </span>
<a name="l00753"></a>00753 <span class="preprocessor">#elif defined   (  __TASKING__  )</span>
<a name="l00754"></a>00754 <span class="preprocessor"></span><span class="preprocessor">  #define __ASM            __asm                                      </span>
<a name="l00755"></a>00755 <span class="preprocessor">  #define __INLINE         inline                                     </span>
<a name="l00757"></a>00757 <span class="preprocessor">#endif</span>
<a name="l00758"></a>00758 <span class="preprocessor"></span>
<a name="l00759"></a>00759 
<a name="l00760"></a>00760 <span class="comment">/* ###################  Compiler specific Intrinsics  ########################### */</span>
<a name="l00761"></a>00761 
<a name="l00762"></a>00762 <span class="preprocessor">#if defined ( __CC_ARM   ) </span><span class="comment">/*------------------RealView Compiler -----------------*/</span>
<a name="l00763"></a>00763 <span class="comment">/* ARM armcc specific functions */</span>
<a name="l00764"></a>00764 
<a name="l00765"></a>00765 <span class="preprocessor">#define __enable_fault_irq                __enable_fiq</span>
<a name="l00766"></a>00766 <span class="preprocessor"></span><span class="preprocessor">#define __disable_fault_irq               __disable_fiq</span>
<a name="l00767"></a>00767 <span class="preprocessor"></span>
<a name="l00768"></a>00768 <span class="preprocessor">#define __NOP                             __nop</span>
<a name="l00769"></a>00769 <span class="preprocessor"></span><span class="preprocessor">#define __WFI                             __wfi</span>
<a name="l00770"></a>00770 <span class="preprocessor"></span><span class="preprocessor">#define __WFE                             __wfe</span>
<a name="l00771"></a>00771 <span class="preprocessor"></span><span class="preprocessor">#define __SEV                             __sev</span>
<a name="l00772"></a>00772 <span class="preprocessor"></span><span class="preprocessor">#define __ISB()                           __isb(0)</span>
<a name="l00773"></a>00773 <span class="preprocessor"></span><span class="preprocessor">#define __DSB()                           __dsb(0)</span>
<a name="l00774"></a>00774 <span class="preprocessor"></span><span class="preprocessor">#define __DMB()                           __dmb(0)</span>
<a name="l00775"></a>00775 <span class="preprocessor"></span><span class="preprocessor">#define __REV                             __rev</span>
<a name="l00776"></a>00776 <span class="preprocessor"></span><span class="preprocessor">#define __RBIT                            __rbit</span>
<a name="l00777"></a>00777 <span class="preprocessor"></span><span class="preprocessor">#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))</span>
<a name="l00778"></a>00778 <span class="preprocessor"></span><span class="preprocessor">#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))</span>
<a name="l00779"></a>00779 <span class="preprocessor"></span><span class="preprocessor">#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))</span>
<a name="l00780"></a>00780 <span class="preprocessor"></span><span class="preprocessor">#define __STREXB(value, ptr)              __strex(value, ptr)</span>
<a name="l00781"></a>00781 <span class="preprocessor"></span><span class="preprocessor">#define __STREXH(value, ptr)              __strex(value, ptr)</span>
<a name="l00782"></a>00782 <span class="preprocessor"></span><span class="preprocessor">#define __STREXW(value, ptr)              __strex(value, ptr)</span>
<a name="l00783"></a>00783 <span class="preprocessor"></span>
<a name="l00784"></a>00784 
<a name="l00785"></a>00785 <span class="comment">/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */</span>
<a name="l00786"></a>00786 <span class="comment">/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */</span>
<a name="l00787"></a>00787 <span class="comment">/* intrinsic void __enable_irq();     */</span>
<a name="l00788"></a>00788 <span class="comment">/* intrinsic void __disable_irq();    */</span>
<a name="l00789"></a>00789 
<a name="l00790"></a>00790 
<a name="l00798"></a>00798 <span class="keyword">extern</span> uint32_t __get_PSP(<span class="keywordtype">void</span>);
<a name="l00799"></a>00799 
<a name="l00808"></a>00808 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_PSP(uint32_t topOfProcStack);
<a name="l00809"></a>00809 
<a name="l00818"></a>00818 <span class="keyword">extern</span> uint32_t __get_MSP(<span class="keywordtype">void</span>);
<a name="l00819"></a>00819 
<a name="l00828"></a>00828 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_MSP(uint32_t topOfMainStack);
<a name="l00829"></a>00829 
<a name="l00838"></a>00838 <span class="keyword">extern</span> uint32_t __REV16(uint16_t value);
<a name="l00839"></a>00839 
<a name="l00848"></a>00848 <span class="keyword">extern</span> int32_t __REVSH(int16_t value);
<a name="l00849"></a>00849 
<a name="l00850"></a>00850 
<a name="l00851"></a>00851 <span class="preprocessor">#if (__ARMCC_VERSION &lt; 400000)</span>
<a name="l00852"></a>00852 <span class="preprocessor"></span>
<a name="l00858"></a>00858 <span class="keyword">extern</span> <span class="keywordtype">void</span> __CLREX(<span class="keywordtype">void</span>);
<a name="l00859"></a>00859 
<a name="l00867"></a>00867 <span class="keyword">extern</span> uint32_t __get_BASEPRI(<span class="keywordtype">void</span>);
<a name="l00868"></a>00868 
<a name="l00876"></a>00876 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_BASEPRI(uint32_t basePri);
<a name="l00877"></a>00877 
<a name="l00885"></a>00885 <span class="keyword">extern</span> uint32_t __get_PRIMASK(<span class="keywordtype">void</span>);
<a name="l00886"></a>00886 
<a name="l00894"></a>00894 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_PRIMASK(uint32_t priMask);
<a name="l00895"></a>00895 
<a name="l00903"></a>00903 <span class="keyword">extern</span> uint32_t __get_FAULTMASK(<span class="keywordtype">void</span>);
<a name="l00904"></a>00904 
<a name="l00912"></a>00912 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_FAULTMASK(uint32_t faultMask);
<a name="l00913"></a>00913 
<a name="l00921"></a>00921 <span class="keyword">extern</span> uint32_t __get_CONTROL(<span class="keywordtype">void</span>);
<a name="l00922"></a>00922 
<a name="l00930"></a>00930 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_CONTROL(uint32_t control);
<a name="l00931"></a>00931 
<a name="l00932"></a>00932 <span class="preprocessor">#else  </span><span class="comment">/* (__ARMCC_VERSION &gt;= 400000)  */</span>
<a name="l00933"></a>00933 
<a name="l00939"></a>00939 <span class="preprocessor">#define __CLREX                           __clrex</span>
<a name="l00940"></a>00940 <span class="preprocessor"></span>
<a name="l00948"></a>00948 <span class="keyword">static</span> __INLINE uint32_t  __get_BASEPRI(<span class="keywordtype">void</span>)
<a name="l00949"></a>00949 {
<a name="l00950"></a>00950   <span class="keyword">register</span> uint32_t __regBasePri         __ASM(<span class="stringliteral">&quot;basepri&quot;</span>);
<a name="l00951"></a>00951   <span class="keywordflow">return</span>(__regBasePri);
<a name="l00952"></a>00952 }
<a name="l00953"></a>00953 
<a name="l00961"></a>00961 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __set_BASEPRI(uint32_t basePri)
<a name="l00962"></a>00962 {
<a name="l00963"></a>00963   <span class="keyword">register</span> uint32_t __regBasePri         __ASM(<span class="stringliteral">&quot;basepri&quot;</span>);
<a name="l00964"></a>00964   __regBasePri = (basePri &amp; 0xff);
<a name="l00965"></a>00965 }
<a name="l00966"></a>00966 
<a name="l00974"></a>00974 <span class="keyword">static</span> __INLINE uint32_t __get_PRIMASK(<span class="keywordtype">void</span>)
<a name="l00975"></a>00975 {
<a name="l00976"></a>00976   <span class="keyword">register</span> uint32_t __regPriMask         __ASM(<span class="stringliteral">&quot;primask&quot;</span>);
<a name="l00977"></a>00977   <span class="keywordflow">return</span>(__regPriMask);
<a name="l00978"></a>00978 }
<a name="l00979"></a>00979 
<a name="l00987"></a>00987 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __set_PRIMASK(uint32_t priMask)
<a name="l00988"></a>00988 {
<a name="l00989"></a>00989   <span class="keyword">register</span> uint32_t __regPriMask         __ASM(<span class="stringliteral">&quot;primask&quot;</span>);
<a name="l00990"></a>00990   __regPriMask = (priMask);
<a name="l00991"></a>00991 }
<a name="l00992"></a>00992 
<a name="l01000"></a>01000 <span class="keyword">static</span> __INLINE uint32_t __get_FAULTMASK(<span class="keywordtype">void</span>)
<a name="l01001"></a>01001 {
<a name="l01002"></a>01002   <span class="keyword">register</span> uint32_t __regFaultMask       __ASM(<span class="stringliteral">&quot;faultmask&quot;</span>);
<a name="l01003"></a>01003   <span class="keywordflow">return</span>(__regFaultMask);
<a name="l01004"></a>01004 }
<a name="l01005"></a>01005 
<a name="l01013"></a>01013 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __set_FAULTMASK(uint32_t faultMask)
<a name="l01014"></a>01014 {
<a name="l01015"></a>01015   <span class="keyword">register</span> uint32_t __regFaultMask       __ASM(<span class="stringliteral">&quot;faultmask&quot;</span>);
<a name="l01016"></a>01016   __regFaultMask = (faultMask &amp; 1);
<a name="l01017"></a>01017 }
<a name="l01018"></a>01018 
<a name="l01026"></a>01026 <span class="keyword">static</span> __INLINE uint32_t __get_CONTROL(<span class="keywordtype">void</span>)
<a name="l01027"></a>01027 {
<a name="l01028"></a>01028   <span class="keyword">register</span> uint32_t __regControl         __ASM(<span class="stringliteral">&quot;control&quot;</span>);
<a name="l01029"></a>01029   <span class="keywordflow">return</span>(__regControl);
<a name="l01030"></a>01030 }
<a name="l01031"></a>01031 
<a name="l01039"></a>01039 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __set_CONTROL(uint32_t control)
<a name="l01040"></a>01040 {
<a name="l01041"></a>01041   <span class="keyword">register</span> uint32_t __regControl         __ASM(<span class="stringliteral">&quot;control&quot;</span>);
<a name="l01042"></a>01042   __regControl = control;
<a name="l01043"></a>01043 }
<a name="l01044"></a>01044 
<a name="l01045"></a>01045 <span class="preprocessor">#endif </span><span class="comment">/* __ARMCC_VERSION  */</span> 
<a name="l01046"></a>01046 
<a name="l01047"></a>01047 
<a name="l01048"></a>01048 
<a name="l01049"></a>01049 <span class="preprocessor">#elif (defined (__ICCARM__)) </span><span class="comment">/*------------------ ICC Compiler -------------------*/</span>
<a name="l01050"></a>01050 <span class="comment">/* IAR iccarm specific functions */</span>
<a name="l01051"></a>01051 
<a name="l01052"></a>01052 <span class="preprocessor">#define __enable_irq                              __enable_interrupt        </span>
<a name="l01053"></a>01053 <span class="preprocessor">#define __disable_irq                             __disable_interrupt       </span>
<a name="l01055"></a>01055 <span class="preprocessor">static __INLINE void __enable_fault_irq()         { __ASM (&quot;cpsie f&quot;); }</span>
<a name="l01056"></a>01056 <span class="preprocessor"></span><span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __disable_fault_irq()        { __ASM (<span class="stringliteral">&quot;cpsid f&quot;</span>); }
<a name="l01057"></a>01057 
<a name="l01058"></a>01058 <span class="preprocessor">#define __NOP                                     __no_operation            </span>
<a name="l01059"></a>01059 <span class="preprocessor">static __INLINE  void __WFI()                     { __ASM (&quot;wfi&quot;); }</span>
<a name="l01060"></a>01060 <span class="preprocessor"></span><span class="keyword">static</span> __INLINE  <span class="keywordtype">void</span> __WFE()                     { __ASM (<span class="stringliteral">&quot;wfe&quot;</span>); }
<a name="l01061"></a>01061 <span class="keyword">static</span> __INLINE  <span class="keywordtype">void</span> __SEV()                     { __ASM (<span class="stringliteral">&quot;sev&quot;</span>); }
<a name="l01062"></a>01062 <span class="keyword">static</span> __INLINE  <span class="keywordtype">void</span> __CLREX()                   { __ASM (<span class="stringliteral">&quot;clrex&quot;</span>); }
<a name="l01063"></a>01063 
<a name="l01064"></a>01064 <span class="comment">/* intrinsic void __ISB(void)                                     */</span>
<a name="l01065"></a>01065 <span class="comment">/* intrinsic void __DSB(void)                                     */</span>
<a name="l01066"></a>01066 <span class="comment">/* intrinsic void __DMB(void)                                     */</span>
<a name="l01067"></a>01067 <span class="comment">/* intrinsic void __set_PRIMASK();                                */</span>
<a name="l01068"></a>01068 <span class="comment">/* intrinsic void __get_PRIMASK();                                */</span>
<a name="l01069"></a>01069 <span class="comment">/* intrinsic void __set_FAULTMASK();                              */</span>
<a name="l01070"></a>01070 <span class="comment">/* intrinsic void __get_FAULTMASK();                              */</span>
<a name="l01071"></a>01071 <span class="comment">/* intrinsic uint32_t __REV(uint32_t value);                      */</span>
<a name="l01072"></a>01072 <span class="comment">/* intrinsic uint32_t __REVSH(uint32_t value);                    */</span>
<a name="l01073"></a>01073 <span class="comment">/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */</span>
<a name="l01074"></a>01074 <span class="comment">/* intrinsic unsigned long __LDREX(unsigned long *);              */</span>
<a name="l01075"></a>01075 
<a name="l01076"></a>01076 
<a name="l01084"></a>01084 <span class="keyword">extern</span> uint32_t __get_PSP(<span class="keywordtype">void</span>);
<a name="l01085"></a>01085 
<a name="l01094"></a>01094 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_PSP(uint32_t topOfProcStack);
<a name="l01095"></a>01095 
<a name="l01104"></a>01104 <span class="keyword">extern</span> uint32_t __get_MSP(<span class="keywordtype">void</span>);
<a name="l01105"></a>01105 
<a name="l01114"></a>01114 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_MSP(uint32_t topOfMainStack);
<a name="l01115"></a>01115 
<a name="l01124"></a>01124 <span class="keyword">extern</span> uint32_t __REV16(uint16_t value);
<a name="l01125"></a>01125 
<a name="l01134"></a>01134 <span class="keyword">extern</span> uint32_t __RBIT(uint32_t value);
<a name="l01135"></a>01135 
<a name="l01144"></a>01144 <span class="keyword">extern</span> uint8_t __LDREXB(uint8_t *addr);
<a name="l01145"></a>01145 
<a name="l01154"></a>01154 <span class="keyword">extern</span> uint16_t __LDREXH(uint16_t *addr);
<a name="l01155"></a>01155 
<a name="l01164"></a>01164 <span class="keyword">extern</span> uint32_t __LDREXW(uint32_t *addr);
<a name="l01165"></a>01165 
<a name="l01175"></a>01175 <span class="keyword">extern</span> uint32_t __STREXB(uint8_t value, uint8_t *addr);
<a name="l01176"></a>01176 
<a name="l01186"></a>01186 <span class="keyword">extern</span> uint32_t __STREXH(uint16_t value, uint16_t *addr);
<a name="l01187"></a>01187 
<a name="l01197"></a>01197 <span class="keyword">extern</span> uint32_t __STREXW(uint32_t value, uint32_t *addr);
<a name="l01198"></a>01198 
<a name="l01199"></a>01199 
<a name="l01200"></a>01200 
<a name="l01201"></a>01201 <span class="preprocessor">#elif (defined (__GNUC__)) </span><span class="comment">/*------------------ GNU Compiler ---------------------*/</span>
<a name="l01202"></a>01202 <span class="comment">/* GNU gcc specific functions */</span>
<a name="l01203"></a>01203 
<a name="l01204"></a>01204 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __enable_irq()               { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;cpsie i&quot;</span>); }
<a name="l01205"></a>01205 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __disable_irq()              { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;cpsid i&quot;</span>); }
<a name="l01206"></a>01206 
<a name="l01207"></a>01207 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __enable_fault_irq()         { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;cpsie f&quot;</span>); }
<a name="l01208"></a>01208 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __disable_fault_irq()        { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;cpsid f&quot;</span>); }
<a name="l01209"></a>01209 
<a name="l01210"></a>01210 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __NOP()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;nop&quot;</span>); }
<a name="l01211"></a>01211 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __WFI()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;wfi&quot;</span>); }
<a name="l01212"></a>01212 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __WFE()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;wfe&quot;</span>); }
<a name="l01213"></a>01213 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __SEV()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;sev&quot;</span>); }
<a name="l01214"></a>01214 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __ISB()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;isb&quot;</span>); }
<a name="l01215"></a>01215 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __DSB()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;dsb&quot;</span>); }
<a name="l01216"></a>01216 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __DMB()                      { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;dmb&quot;</span>); }
<a name="l01217"></a>01217 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> __CLREX()                    { __ASM <span class="keyword">volatile</span> (<span class="stringliteral">&quot;clrex&quot;</span>); }
<a name="l01218"></a>01218 
<a name="l01219"></a>01219 
<a name="l01227"></a>01227 <span class="keyword">extern</span> uint32_t __get_PSP(<span class="keywordtype">void</span>);
<a name="l01228"></a>01228 
<a name="l01237"></a>01237 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_PSP(uint32_t topOfProcStack);
<a name="l01238"></a>01238 
<a name="l01247"></a>01247 <span class="keyword">extern</span> uint32_t __get_MSP(<span class="keywordtype">void</span>);
<a name="l01248"></a>01248 
<a name="l01257"></a>01257 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_MSP(uint32_t topOfMainStack);
<a name="l01258"></a>01258 
<a name="l01266"></a>01266 <span class="keyword">extern</span> uint32_t __get_BASEPRI(<span class="keywordtype">void</span>);
<a name="l01267"></a>01267 
<a name="l01275"></a>01275 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_BASEPRI(uint32_t basePri);
<a name="l01276"></a>01276 
<a name="l01284"></a>01284 <span class="keyword">extern</span> uint32_t  __get_PRIMASK(<span class="keywordtype">void</span>);
<a name="l01285"></a>01285 
<a name="l01293"></a>01293 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_PRIMASK(uint32_t priMask);
<a name="l01294"></a>01294 
<a name="l01302"></a>01302 <span class="keyword">extern</span> uint32_t __get_FAULTMASK(<span class="keywordtype">void</span>);
<a name="l01303"></a>01303 
<a name="l01311"></a>01311 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_FAULTMASK(uint32_t faultMask);
<a name="l01312"></a>01312 
<a name="l01320"></a>01320 <span class="keyword">extern</span> uint32_t __get_CONTROL(<span class="keywordtype">void</span>);
<a name="l01321"></a>01321 
<a name="l01329"></a>01329 <span class="keyword">extern</span> <span class="keywordtype">void</span> __set_CONTROL(uint32_t control);
<a name="l01330"></a>01330 
<a name="l01339"></a>01339 <span class="keyword">extern</span> uint32_t __REV(uint32_t value);
<a name="l01340"></a>01340 
<a name="l01349"></a>01349 <span class="keyword">extern</span> uint32_t __REV16(uint16_t value);
<a name="l01350"></a>01350 
<a name="l01359"></a>01359 <span class="keyword">extern</span> int32_t __REVSH(int16_t value);
<a name="l01360"></a>01360 
<a name="l01369"></a>01369 <span class="keyword">extern</span> uint32_t __RBIT(uint32_t value);
<a name="l01370"></a>01370 
<a name="l01379"></a>01379 <span class="keyword">extern</span> uint8_t __LDREXB(uint8_t *addr);
<a name="l01380"></a>01380 
<a name="l01389"></a>01389 <span class="keyword">extern</span> uint16_t __LDREXH(uint16_t *addr);
<a name="l01390"></a>01390 
<a name="l01399"></a>01399 <span class="keyword">extern</span> uint32_t __LDREXW(uint32_t *addr);
<a name="l01400"></a>01400 
<a name="l01410"></a>01410 <span class="keyword">extern</span> uint32_t __STREXB(uint8_t value, uint8_t *addr);
<a name="l01411"></a>01411 
<a name="l01421"></a>01421 <span class="keyword">extern</span> uint32_t __STREXH(uint16_t value, uint16_t *addr);
<a name="l01422"></a>01422 
<a name="l01432"></a>01432 <span class="keyword">extern</span> uint32_t __STREXW(uint32_t value, uint32_t *addr);
<a name="l01433"></a>01433 
<a name="l01434"></a>01434 
<a name="l01435"></a>01435 <span class="preprocessor">#elif (defined (__TASKING__)) </span><span class="comment">/*------------------ TASKING Compiler ---------------------*/</span>
<a name="l01436"></a>01436 <span class="comment">/* TASKING carm specific functions */</span>
<a name="l01437"></a>01437 
<a name="l01438"></a>01438 <span class="comment">/*</span>
<a name="l01439"></a>01439 <span class="comment"> * The CMSIS functions have been implemented as intrinsics in the compiler.</span>
<a name="l01440"></a>01440 <span class="comment"> * Please use &quot;carm -?i&quot; to get an up to date list of all instrinsics,</span>
<a name="l01441"></a>01441 <span class="comment"> * Including the CMSIS ones.</span>
<a name="l01442"></a>01442 <span class="comment"> */</span>
<a name="l01443"></a>01443 
<a name="l01444"></a>01444 <span class="preprocessor">#endif</span>
<a name="l01445"></a>01445 <span class="preprocessor"></span>
<a name="l01446"></a>01446 
<a name="l01454"></a>01454 
<a name="l01455"></a>01455 <span class="comment">/* ##########################   NVIC functions  #################################### */</span>
<a name="l01456"></a>01456 
<a name="l01468"></a>01468 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<a name="l01469"></a>01469 {
<a name="l01470"></a>01470   uint32_t reg_value;
<a name="l01471"></a>01471   uint32_t PriorityGroupTmp = (PriorityGroup &amp; 0x07);                         <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01472"></a>01472   
<a name="l01473"></a>01473   reg_value  =  <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR;                                                   <span class="comment">/* read old register configuration    */</span>
<a name="l01474"></a>01474   reg_value &amp;= ~(<a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22">SCB_AIRCR_VECTKEY_Msk</a> | <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>);             <span class="comment">/* clear bits to change               */</span>
<a name="l01475"></a>01475   reg_value  =  (reg_value                       |
<a name="l01476"></a>01476                 (0x5FA &lt;&lt; <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>) | 
<a name="l01477"></a>01477                 (PriorityGroupTmp &lt;&lt; 8));                                     <span class="comment">/* Insert write key and priorty group */</span>
<a name="l01478"></a>01478   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR =  reg_value;
<a name="l01479"></a>01479 }
<a name="l01480"></a>01480 
<a name="l01489"></a>01489 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPriorityGrouping(<span class="keywordtype">void</span>)
<a name="l01490"></a>01490 {
<a name="l01491"></a>01491   <span class="keywordflow">return</span> ((<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR &amp; <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>) &gt;&gt; <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8">SCB_AIRCR_PRIGROUP_Pos</a>);   <span class="comment">/* read priority grouping field */</span>
<a name="l01492"></a>01492 }
<a name="l01493"></a>01493 
<a name="l01502"></a>01502 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_EnableIRQ(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> <a class="code" href="group___l_p_c17xx___system.html#ga666eb0caeb12ec0e281415592ae89083" title="IRQ interrupt source definition.">IRQn</a>)
<a name="l01503"></a>01503 {
<a name="l01504"></a>01504   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISER[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___l_p_c17xx___system.html#ga666eb0caeb12ec0e281415592ae89083" title="IRQ interrupt source definition.">IRQn</a>) &amp; 0x1F)); <span class="comment">/* enable interrupt */</span>
<a name="l01505"></a>01505 }
<a name="l01506"></a>01506 
<a name="l01515"></a>01515 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_DisableIRQ(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01516"></a>01516 {
<a name="l01517"></a>01517   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ICER[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___l_p_c17xx___system.html#ga666eb0caeb12ec0e281415592ae89083" title="IRQ interrupt source definition.">IRQn</a>) &amp; 0x1F)); <span class="comment">/* disable interrupt */</span>
<a name="l01518"></a>01518 }
<a name="l01519"></a>01519 
<a name="l01529"></a>01529 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPendingIRQ(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01530"></a>01530 {
<a name="l01531"></a>01531   <span class="keywordflow">return</span>((uint32_t) ((<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISPR[(uint32_t)(IRQn) &gt;&gt; 5] &amp; (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F)))?1:0)); <span class="comment">/* Return 1 if pending else 0 */</span>
<a name="l01532"></a>01532 }
<a name="l01533"></a>01533 
<a name="l01542"></a>01542 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPendingIRQ(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01543"></a>01543 {
<a name="l01544"></a>01544   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISPR[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___l_p_c17xx___system.html#ga666eb0caeb12ec0e281415592ae89083" title="IRQ interrupt source definition.">IRQn</a>) &amp; 0x1F)); <span class="comment">/* set interrupt pending */</span>
<a name="l01545"></a>01545 }
<a name="l01546"></a>01546 
<a name="l01555"></a>01555 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_ClearPendingIRQ(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01556"></a>01556 {
<a name="l01557"></a>01557   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ICPR[((uint32_t)(IRQn) &gt;&gt; 5)] = (1 &lt;&lt; ((uint32_t)(<a class="code" href="group___l_p_c17xx___system.html#ga666eb0caeb12ec0e281415592ae89083" title="IRQ interrupt source definition.">IRQn</a>) &amp; 0x1F)); <span class="comment">/* Clear pending interrupt */</span>
<a name="l01558"></a>01558 }
<a name="l01559"></a>01559 
<a name="l01569"></a>01569 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetActive(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01570"></a>01570 {
<a name="l01571"></a>01571   <span class="keywordflow">return</span>((uint32_t)((<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IABR[(uint32_t)(IRQn) &gt;&gt; 5] &amp; (1 &lt;&lt; ((uint32_t)(IRQn) &amp; 0x1F)))?1:0)); <span class="comment">/* Return 1 if active else 0 */</span>
<a name="l01572"></a>01572 }
<a name="l01573"></a>01573 
<a name="l01586"></a>01586 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SetPriority(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn, uint32_t priority)
<a name="l01587"></a>01587 {
<a name="l01588"></a>01588   <span class="keywordflow">if</span>(IRQn &lt; 0) {
<a name="l01589"></a>01589     <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;SHP[((uint32_t)(IRQn) &amp; 0xF)-4] = ((priority &lt;&lt; (8 - <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) &amp; 0xff); } <span class="comment">/* set Priority for Cortex-M3 System Interrupts */</span>
<a name="l01590"></a>01590   <span class="keywordflow">else</span> {
<a name="l01591"></a>01591     <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IP[(uint32_t)(IRQn)] = ((priority &lt;&lt; (8 - <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) &amp; 0xff);    }        <span class="comment">/* set Priority for device specific Interrupts  */</span>
<a name="l01592"></a>01592 }
<a name="l01593"></a>01593 
<a name="l01609"></a>01609 <span class="keyword">static</span> __INLINE uint32_t NVIC_GetPriority(<a class="code" href="group___l_p_c17xx___system.html#gac3af4a32370fb28c4ade8bf2add80251" title="IRQ interrupt source definition.">IRQn_Type</a> IRQn)
<a name="l01610"></a>01610 {
<a name="l01611"></a>01611 
<a name="l01612"></a>01612   <span class="keywordflow">if</span>(IRQn &lt; 0) {
<a name="l01613"></a>01613     <span class="keywordflow">return</span>((uint32_t)(<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;SHP[((uint32_t)(IRQn) &amp; 0xF)-4] &gt;&gt; (8 - <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));  } <span class="comment">/* get priority for Cortex-M3 system interrupts */</span>
<a name="l01614"></a>01614   <span class="keywordflow">else</span> {
<a name="l01615"></a>01615     <span class="keywordflow">return</span>((uint32_t)(<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IP[(uint32_t)(IRQn)]           &gt;&gt; (8 - <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)));  } <span class="comment">/* get priority for device specific interrupts  */</span>
<a name="l01616"></a>01616 }
<a name="l01617"></a>01617 
<a name="l01618"></a>01618 
<a name="l01634"></a>01634 <span class="keyword">static</span> __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<a name="l01635"></a>01635 {
<a name="l01636"></a>01636   uint32_t PriorityGroupTmp = (PriorityGroup &amp; 0x07);          <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01637"></a>01637   uint32_t PreemptPriorityBits;
<a name="l01638"></a>01638   uint32_t SubPriorityBits;
<a name="l01639"></a>01639 
<a name="l01640"></a>01640   PreemptPriorityBits = ((7 - PriorityGroupTmp) &gt; <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) ? <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> : 7 - PriorityGroupTmp;
<a name="l01641"></a>01641   SubPriorityBits     = ((PriorityGroupTmp + <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) &lt; 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;
<a name="l01642"></a>01642  
<a name="l01643"></a>01643   <span class="keywordflow">return</span> (
<a name="l01644"></a>01644            ((PreemptPriority &amp; ((1 &lt;&lt; (PreemptPriorityBits)) - 1)) &lt;&lt; SubPriorityBits) |
<a name="l01645"></a>01645            ((SubPriority     &amp; ((1 &lt;&lt; (SubPriorityBits    )) - 1)))
<a name="l01646"></a>01646          );
<a name="l01647"></a>01647 }
<a name="l01648"></a>01648 
<a name="l01649"></a>01649 
<a name="l01665"></a>01665 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<a name="l01666"></a>01666 {
<a name="l01667"></a>01667   uint32_t PriorityGroupTmp = (PriorityGroup &amp; 0x07);          <span class="comment">/* only values 0..7 are used          */</span>
<a name="l01668"></a>01668   uint32_t PreemptPriorityBits;
<a name="l01669"></a>01669   uint32_t SubPriorityBits;
<a name="l01670"></a>01670 
<a name="l01671"></a>01671   PreemptPriorityBits = ((7 - PriorityGroupTmp) &gt; __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
<a name="l01672"></a>01672   SubPriorityBits     = ((PriorityGroupTmp + <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) &lt; 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___c_m_s_i_s___c_m3__core__definitions.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;
<a name="l01673"></a>01673   
<a name="l01674"></a>01674   *pPreemptPriority = (Priority &gt;&gt; SubPriorityBits) &amp; ((1 &lt;&lt; (PreemptPriorityBits)) - 1);
<a name="l01675"></a>01675   *pSubPriority     = (Priority                   ) &amp; ((1 &lt;&lt; (SubPriorityBits    )) - 1);
<a name="l01676"></a>01676 }
<a name="l01677"></a>01677 
<a name="l01678"></a>01678 
<a name="l01679"></a>01679 
<a name="l01680"></a>01680 <span class="comment">/* ##################################    SysTick function  ############################################ */</span>
<a name="l01681"></a>01681 
<a name="l01682"></a>01682 <span class="preprocessor">#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)</span>
<a name="l01683"></a>01683 <span class="preprocessor"></span>
<a name="l01694"></a>01694 <span class="keyword">static</span> __INLINE uint32_t SysTick_Config(uint32_t ticks)
<a name="l01695"></a>01695 { 
<a name="l01696"></a>01696   <span class="keywordflow">if</span> (ticks &gt; <a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a>)  <span class="keywordflow">return</span> (1);            <span class="comment">/* Reload value impossible */</span>
<a name="l01697"></a>01697                                                                
<a name="l01698"></a>01698   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;LOAD  = (ticks &amp; <a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a>) - 1;      <span class="comment">/* set reload register */</span>
<a name="l01699"></a>01699   NVIC_SetPriority (<a class="code" href="group___l_p_c17xx___system.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>, (1&lt;&lt;__NVIC_PRIO_BITS) - 1);  <span class="comment">/* set Priority for Cortex-M0 System Interrupts */</span>
<a name="l01700"></a>01700   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;VAL   = 0;                                          <span class="comment">/* Load the SysTick Counter Value */</span>
<a name="l01701"></a>01701   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;CTRL  = <a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a> | 
<a name="l01702"></a>01702                    <a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a>   | 
<a name="l01703"></a>01703                    <a class="code" href="group___c_m_s_i_s___c_m3___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a>;                    <span class="comment">/* Enable SysTick IRQ and SysTick Timer */</span>
<a name="l01704"></a>01704   <span class="keywordflow">return</span> (0);                                                  <span class="comment">/* Function successful */</span>
<a name="l01705"></a>01705 }
<a name="l01706"></a>01706 
<a name="l01707"></a>01707 <span class="preprocessor">#endif</span>
<a name="l01708"></a>01708 <span class="preprocessor"></span>
<a name="l01709"></a>01709 
<a name="l01710"></a>01710 
<a name="l01711"></a>01711 
<a name="l01712"></a>01712 <span class="comment">/* ##################################    Reset function  ############################################ */</span>
<a name="l01713"></a>01713 
<a name="l01719"></a>01719 <span class="keyword">static</span> __INLINE <span class="keywordtype">void</span> NVIC_SystemReset(<span class="keywordtype">void</span>)
<a name="l01720"></a>01720 {
<a name="l01721"></a>01721   <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR  = ((0x5FA &lt;&lt; <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>)      | 
<a name="l01722"></a>01722                  (<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR &amp; <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>) | 
<a name="l01723"></a>01723                  <a class="code" href="group___c_m_s_i_s___c_m3___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a>);                   <span class="comment">/* Keep priority group unchanged */</span>
<a name="l01724"></a>01724   __DSB();                                                     <span class="comment">/* Ensure completion of memory access */</span>              
<a name="l01725"></a>01725   <span class="keywordflow">while</span>(1);                                                    <span class="comment">/* wait until reset */</span>
<a name="l01726"></a>01726 }
<a name="l01727"></a>01727  <span class="comment">/* end of group CMSIS_CM3_Core_FunctionInterface */</span>
<a name="l01729"></a>01729 
<a name="l01730"></a>01730 
<a name="l01731"></a>01731 
<a name="l01732"></a>01732 <span class="comment">/* ##################################### Debug In/Output function ########################################### */</span>
<a name="l01733"></a>01733 
<a name="l01741"></a>01741 
<a name="l01742"></a>01742 <span class="keyword">extern</span> <span class="keyword">volatile</span> <span class="keywordtype">int</span> <a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gacf1fe3063cedf11b6e6f7cb0dd7c1a51">ITM_RxBuffer</a>;                    
<a name="l01743"></a><a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gaa822cb398ee022b59e9e6c5d7bbb228a">01743</a> <span class="preprocessor">#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 </span>
<a name="l01756"></a>01756 <span class="preprocessor">static __INLINE uint32_t ITM_SendChar (uint32_t ch)</span>
<a name="l01757"></a>01757 <span class="preprocessor"></span>{
<a name="l01758"></a>01758   <span class="keywordflow">if</span> ((<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gab6e30a2b802d9021619dbb0be7f5d63d">CoreDebug</a>-&gt;DEMCR &amp; <a class="code" href="group___c_m_s_i_s___c_m3___core_debug.html#ga5e99652c1df93b441257389f49407834">CoreDebug_DEMCR_TRCENA_Msk</a>)  &amp;&amp;      <span class="comment">/* Trace enabled */</span>
<a name="l01759"></a>01759       (<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>-&gt;TCR &amp; <a class="code" href="group___c_m_s_i_s___c_m3___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9">ITM_TCR_ITMENA_Msk</a>)                  &amp;&amp;      <span class="comment">/* ITM enabled */</span>
<a name="l01760"></a>01760       (<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>-&gt;TER &amp; (1ul &lt;&lt; 0)        )                    )     <span class="comment">/* ITM Port #0 enabled */</span>
<a name="l01761"></a>01761   {
<a name="l01762"></a>01762     <span class="keywordflow">while</span> (<a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>-&gt;PORT[0].u32 == 0);
<a name="l01763"></a>01763     <a class="code" href="group___c_m_s_i_s___c_m3__core__register.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>-&gt;PORT[0].u8 = (uint8_t) ch;
<a name="l01764"></a>01764   }  
<a name="l01765"></a>01765   <span class="keywordflow">return</span> (ch);
<a name="l01766"></a>01766 }
<a name="l01767"></a>01767 
<a name="l01768"></a>01768 
<a name="l01778"></a>01778 <span class="keyword">static</span> __INLINE <span class="keywordtype">int</span> ITM_ReceiveChar (<span class="keywordtype">void</span>) {
<a name="l01779"></a>01779   <span class="keywordtype">int</span> ch = -1;                               <span class="comment">/* no character available */</span>
<a name="l01780"></a>01780 
<a name="l01781"></a>01781   <span class="keywordflow">if</span> (ITM_RxBuffer != <a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>) {
<a name="l01782"></a>01782     ch = <a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gacf1fe3063cedf11b6e6f7cb0dd7c1a51">ITM_RxBuffer</a>;
<a name="l01783"></a>01783     ITM_RxBuffer = <a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>;       <span class="comment">/* ready for next character */</span>
<a name="l01784"></a>01784   }
<a name="l01785"></a>01785   
<a name="l01786"></a>01786   <span class="keywordflow">return</span> (ch); 
<a name="l01787"></a>01787 }
<a name="l01788"></a>01788 
<a name="l01789"></a>01789 
<a name="l01798"></a>01798 <span class="keyword">static</span> __INLINE <span class="keywordtype">int</span> ITM_CheckChar (<span class="keywordtype">void</span>) {
<a name="l01799"></a>01799 
<a name="l01800"></a>01800   <span class="keywordflow">if</span> (ITM_RxBuffer == <a class="code" href="group___c_m_s_i_s___c_m3___core_debug_interface.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>) {
<a name="l01801"></a>01801     <span class="keywordflow">return</span> (0);                                 <span class="comment">/* no character available */</span>
<a name="l01802"></a>01802   } <span class="keywordflow">else</span> {
<a name="l01803"></a>01803     <span class="keywordflow">return</span> (1);                                 <span class="comment">/*    character available */</span>
<a name="l01804"></a>01804   }
<a name="l01805"></a>01805 }
<a name="l01806"></a>01806  <span class="comment">/* end of group CMSIS_CM3_core_DebugInterface */</span>
<a name="l01808"></a>01808 
<a name="l01809"></a>01809 
<a name="l01810"></a>01810 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l01811"></a>01811 <span class="preprocessor"></span>}
<a name="l01812"></a>01812 <span class="preprocessor">#endif</span>
<a name="l01813"></a>01813 <span class="preprocessor"></span> <span class="comment">/* end of group CMSIS_CM3_core_definitions */</span>
<a name="l01815"></a>01815 
<a name="l01816"></a>01816 <span class="preprocessor">#endif </span><span class="comment">/* __CM3_CORE_H__ */</span>
<a name="l01817"></a>01817 
<a name="l01818"></a>01818 <span class="comment">/*lint -restore */</span>
</pre></div></div><!-- contents -->


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